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fine tuning on mcnc example script so that we can run run_modelsim.py --runsim

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tangxifan 2020-04-22 21:44:52 -06:00
parent f9fcc6b471
commit df85175765
1 changed files with 1 additions and 1 deletions
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openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
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@ -45,7 +45,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --inc
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./simulation_deck_info.ini
# Write the SDC files for PnR backend # Write the SDC files for PnR backend
# - Turn on every options here # - Turn on every options here