Correction top module

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c

@@ -1075,16 +1075,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
   for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
     switch (rr_chan.get_node(itrack)->direction) {
     case INC_DIRECTION:
-      fprintf(fp, "%s, ",
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ".in%d (",itrack);
+    }
+      fprintf(fp, "%s",
               gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
                                                        x, y, itrack, OUT_PORT));
-      fprintf(fp, "\n");
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ")");
+    }
+      fprintf(fp, ",\n");
       break;
     case DEC_DIRECTION:
-      fprintf(fp, "%s, ",
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ".out%d (",itrack);
+    }
+      fprintf(fp, "%s",
               gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
                                                        x, y, itrack, IN_PORT));
-      fprintf(fp, "\n");
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ")");
+    }
+      fprintf(fp, ",\n");
       break;
     default:
       vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n",
@@ -1103,16 +1115,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
   for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
     switch (rr_chan.get_node(itrack)->direction) {
     case INC_DIRECTION:
-      fprintf(fp, "%s, ",
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ".out%d (",itrack);
+    }
+      fprintf(fp, "%s",
               gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
                                                        x, y, itrack, IN_PORT));
-      fprintf(fp, "\n");
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ")");
+    }
+      fprintf(fp, ",\n");
       break;
     case DEC_DIRECTION:
-      fprintf(fp, "%s, ",
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ".in%d (",itrack);
+    }
+      fprintf(fp, "%s",
               gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack),
                                                        x, y, itrack, OUT_PORT));
-      fprintf(fp, "\n");
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ")");
+    }
+      fprintf(fp, ",\n");
       break;
     default:
       vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n",
@@ -1125,9 +1149,16 @@ void dump_compact_verilog_defined_one_channel(FILE* fp,
 
   /* output at middle point */
   for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) {
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ".mid_out%d (", 
+              itrack);
+    }
     fprintf(fp, "%s_%d__%d__midout_%lu_ ", 
             convert_chan_type_to_string(rr_chan.get_type()),
             x, y, itrack);
+    if (true == is_explicit_mapping) {
+      fprintf(fp, ")");
+    }
     if (itrack < rr_chan.get_chan_width() - 1) {
       fprintf(fp, ",");
     }

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c

@@ -337,7 +337,7 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
   fprintf(fp, "\n");
 
   dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT,
-                                is_explicit_mapping);
+                                false);
 
   fprintf(fp, ");\n");
 

vpr7_x2p/vpr/regression_verilog.sh

@@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
 cd -
 
 # Run VPR  
-./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy 
+./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
 
 cd $fpga_flow_scripts
 perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path