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use user defined critical path delay in SDC generation

This commit is contained in:
tangxifan 2020-02-28 11:24:39 -07:00
parent 092e10afda
commit de8425874c
3 changed files with 15 additions and 15 deletions
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4
openfpga/src/base/openfpga_sdc.cpp
View File

@ -64,8 +64,8 @@ void write_pnr_sdc(OpenfpgaContext& openfpga_ctx,
/* Execute only when sdc is enabled */
if (true == options.generate_sdc_pnr()) {
print_pnr_sdc(options,
0, /* TODO: add critical path stats to OpenFPGA context */
//openfpga_ctx.vpr_timing_annotation().critical_path_delay();
1./openfpga_ctx.arch().sim_setting.programming_clock_frequency(),
1./openfpga_ctx.arch().sim_setting.operating_clock_frequency(),
g_vpr_ctx.device(),
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(),

23
openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
View File

@ -35,12 +35,6 @@
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Local variables
*******************************************************************/
constexpr float SDC_FIXED_PROG_CLOCK_PERIOD = 100;
constexpr float SDC_FIXED_CLOCK_PERIOD = 10;
/********************************************************************
* Print a SDC file to constrain the global ports of FPGA fabric
* in particular clock ports
@ -50,7 +44,8 @@ constexpr float SDC_FIXED_CLOCK_PERIOD = 10;
*******************************************************************/
static
void print_pnr_sdc_global_ports(const std::string& sdc_dir,
const float& critical_path_delay,
const float& programming_critical_path_delay,
const float& operating_critical_path_delay,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports) {
@ -76,11 +71,11 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
continue;
}
/* Reach here, it means a clock port and we need print constraints */
float clock_period = critical_path_delay;
float clock_period = operating_critical_path_delay;
/* For programming clock, we give a fixed period */
if (true == circuit_lib.port_is_prog(clock_port)) {
clock_period = SDC_FIXED_PROG_CLOCK_PERIOD;
clock_period = programming_critical_path_delay;
/* Print comments */
fp << "##################################################" << std::endl;
fp << "# Create programmable clock " << std::endl;
@ -118,7 +113,7 @@ void print_pnr_sdc_global_ports(const std::string& sdc_dir,
fp << "##################################################" << std::endl;
/* Reach here, it means a non-clock global port and we need print constraints */
float clock_period = SDC_FIXED_CLOCK_PERIOD;
float clock_period = operating_critical_path_delay;
for (const size_t& pin : circuit_lib.pins(global_port)) {
BasicPort port_to_constrain(circuit_lib.port_prefix(global_port), pin, pin);
fp << "create_clock ";
@ -343,7 +338,8 @@ void print_pnr_sdc_compact_routing_disable_switch_block_outputs(const std::strin
* 4. Design constraints for breaking the combinational loops in FPGA fabric
*******************************************************************/
void print_pnr_sdc(const PnrSdcOption& sdc_options,
const float& critical_path_delay,
const float& programming_critical_path_delay,
const float& operating_critical_path_delay,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb,
@ -355,7 +351,10 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
/* Constrain global ports */
if (true == sdc_options.constrain_global_port()) {
print_pnr_sdc_global_ports(sdc_options.sdc_dir(), critical_path_delay, circuit_lib, global_ports);
print_pnr_sdc_global_ports(sdc_options.sdc_dir(),
programming_critical_path_delay,
operating_critical_path_delay,
circuit_lib, global_ports);
}
std::string top_module_name = generate_fpga_top_module_name();

3
openfpga/src/fpga_sdc/pnr_sdc_writer.h
View File

@ -22,7 +22,8 @@
namespace openfpga {
void print_pnr_sdc(const PnrSdcOption& sdc_options,
const float& critical_path_delay,
const float& programming_critical_path_delay,
const float& operating_critical_path_delay,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb,