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[Script] Correct naming for clocks in shifter register chain defined in simulation setting files

This commit is contained in:
tangxifan 2021-10-06 13:36:35 -07:00
parent a1eaacf5a8
commit dc5aedc393
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
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@ -8,8 +8,8 @@
<clock_setting>
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
<programming frequency="100e6">
<clock name="bl_shift_register_clk" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
<clock name="wl_shift_register_clk" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
<clock name="bl_sr_clock" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
<clock name="wl_sr_clock" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
</programming>
</clock_setting>
<simulator_option>