From dc5aedc39327dddcd247ffa91ad369be5a13b220 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 6 Oct 2021 13:36:35 -0700
Subject: [PATCH] [Script] Correct naming for clocks in shifter register chain
 defined in simulation setting files

---
 .../fixed_shift_register_sim_openfpga.xml                     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml b/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
index 740e00a1c..a3b5b88de 100644
--- a/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
+++ b/openfpga_flow/openfpga_simulation_settings/fixed_shift_register_sim_openfpga.xml
@@ -8,8 +8,8 @@
   <clock_setting>
     <operating frequency="auto" num_cycles="auto" slack="0.2"/>
     <programming frequency="100e6">
-      <clock name="bl_shift_register_clk" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
-      <clock name="wl_shift_register_clk" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
+      <clock name="bl_sr_clock" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
+      <clock name="wl_sr_clock" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
     </programming>
   </clock_setting>
   <simulator_option>