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update tests to use no_ff_map and remove tests that need async set/reset for now

This commit is contained in:
Tarachand Pagarani 2021-03-10 10:04:45 -08:00
parent 608bd1f658
commit db8ea86b2f
3 changed files with 6 additions and 2 deletions
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2
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
yosys_args = -no_adder -family qlf_k4n8 yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml

4
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -63,6 +63,7 @@ bench5_top = rs_decoder_top
bench6_top = top_module bench6_top = top_module
bench7_top = sha256 bench7_top = sha256
bench8_top = cavlc_top bench8_top = cavlc_top
#bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
bench9_top = cf_fft_256_8 bench9_top = cf_fft_256_8
#bench10_top = counter120bitx5 #bench10_top = counter120bitx5
#bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
@ -71,8 +72,11 @@ bench12_top = dct_mac
bench13_top = des_perf bench13_top = des_perf
bench14_top = diffeq_f_systemC bench14_top = diffeq_f_systemC
bench15_top = i2c_master_top bench15_top = i2c_master_top
#bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
bench16_top = iir bench16_top = iir
#bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
bench17_top = jpeg_qnr bench17_top = jpeg_qnr
#bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
bench18_top = multi_enc_decx2x4 bench18_top = multi_enc_decx2x4
# sdc_controller requires 4 clocks # sdc_controller requires 4 clocks
#bench19_top = sdc_controller #bench19_top = sdc_controller

2
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
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@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
openfpga_vpr_circuit_format=eblif openfpga_vpr_circuit_format=eblif
yosys_args = -family qlf_k4n8 yosys_args = -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml