[test] typo
This commit is contained in:
parent
7996de3fe6
commit
db12532eb8
|
@ -27,7 +27,7 @@ openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
|
||||||
openfpga_verilog_testbench_options=--explicit_port_mapping
|
openfpga_verilog_testbench_options=--explicit_port_mapping
|
||||||
|
|
||||||
[ARCHITECTURES]
|
[ARCHITECTURES]
|
||||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
|
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBl_40nm.xml
|
||||||
|
|
||||||
[BENCHMARKS]
|
[BENCHMARKS]
|
||||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
|
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
|
||||||
|
|
|
@ -1 +1 @@
|
||||||
<tiles style="top_left"/>
|
<tiles style="bottom_left"/>
|
||||||
|
|
Loading…
Reference in New Issue