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[Tool] Encapulate search function in PinConstraint data structure

This commit is contained in:
tangxifan 2021-04-17 17:31:55 -06:00
parent da619fabe7
commit d95a1e2776
4 changed files with 19 additions and 21 deletions
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11
libopenfpga/libpcf/src/pin_constraints.cpp
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@ -38,6 +38,17 @@ std::string PinConstraints::net(const PinConstraintId& pin_constraint_id) const
return pin_constraint_nets_[pin_constraint_id]; return pin_constraint_nets_[pin_constraint_id];
} }
std::string PinConstraints::pin_net(const openfpga::BasicPort& pin) const {
std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET);
for (const PinConstraintId& pin_constraint : pin_constraints()) {
if (pin == pin_constraint_pins_[pin_constraint]) {
constrained_net_name = net(pin_constraint);
break;
}
}
return constrained_net_name;
}
bool PinConstraints::empty() const { bool PinConstraints::empty() const {
return 0 == pin_constraint_ids_.size(); return 0 == pin_constraint_ids_.size();
} }

5
libopenfpga/libpcf/src/pin_constraints.h
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@ -52,6 +52,11 @@ class PinConstraints {
/* Get the net to be constrained */ /* Get the net to be constrained */
std::string net(const PinConstraintId& pin_constraint_id) const; std::string net(const PinConstraintId& pin_constraint_id) const;
/* Find the net that is constrained on a pin
* TODO: this function will only return the first net found in the constraint list
*/
std::string pin_net(const openfpga::BasicPort& pin) const;
/* Check if there are any pin constraints */ /* Check if there are any pin constraints */
bool empty() const; bool empty() const;

16
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -135,13 +135,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
BasicPort module_clock_pin(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]); BasicPort module_clock_pin(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
/* If the clock port name is in the pin constraints, we should wire it to the constrained pin */ /* If the clock port name is in the pin constraints, we should wire it to the constrained pin */
std::string constrained_net_name; std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin);
for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
if (module_clock_pin == pin_constraints.pin(pin_constraint)) {
constrained_net_name = pin_constraints.net(pin_constraint);
break;
}
}
/* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */ /* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */
if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name) if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name)
@ -179,13 +173,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
module_global_port.pins()[pin_id]); module_global_port.pins()[pin_id]);
/* If the global port name is in the pin constraints, we should wire it to the constrained pin */ /* If the global port name is in the pin constraints, we should wire it to the constrained pin */
std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET); std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
if (module_global_pin == pin_constraints.pin(pin_constraint)) {
constrained_net_name = pin_constraints.net(pin_constraint);
break;
}
}
/* - If constrained to a given net in the benchmark, we connect the global pin to the net /* - If constrained to a given net in the benchmark, we connect the global pin to the net
* - If constrained to an open net in the benchmark, we assign it to a default value * - If constrained to an open net in the benchmark, we assign it to a default value

8
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -385,13 +385,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
/* Regular reset port can be mapped by a net from user design */ /* Regular reset port can be mapped by a net from user design */
if (false == fabric_global_port_info.global_port_is_prog(fabric_global_port)) { if (false == fabric_global_port_info.global_port_is_prog(fabric_global_port)) {
/* If the global port name is in the pin constraints, we should wire it to the constrained pin */ /* If the global port name is in the pin constraints, we should wire it to the constrained pin */
std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET); std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
if (module_global_pin == pin_constraints.pin(pin_constraint)) {
constrained_net_name = pin_constraints.net(pin_constraint);
break;
}
}
/* - If constrained to a given net in the benchmark, we connect the global pin to the net */ /* - If constrained to a given net in the benchmark, we connect the global pin to the net */
if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) { if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) {