diff --git a/libopenfpga/libpcf/src/pin_constraints.cpp b/libopenfpga/libpcf/src/pin_constraints.cpp
index 4f7a701a7..e48d8bf57 100644
--- a/libopenfpga/libpcf/src/pin_constraints.cpp
+++ b/libopenfpga/libpcf/src/pin_constraints.cpp
@@ -38,6 +38,17 @@ std::string PinConstraints::net(const PinConstraintId& pin_constraint_id) const
   return pin_constraint_nets_[pin_constraint_id]; 
 }
 
+std::string PinConstraints::pin_net(const openfpga::BasicPort& pin) const {
+  std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET);
+  for (const PinConstraintId& pin_constraint : pin_constraints()) {
+    if (pin == pin_constraint_pins_[pin_constraint]) {
+      constrained_net_name = net(pin_constraint); 
+      break;
+    }
+  }
+  return constrained_net_name;
+}
+
 bool PinConstraints::empty() const {
   return 0 == pin_constraint_ids_.size();
 }
diff --git a/libopenfpga/libpcf/src/pin_constraints.h b/libopenfpga/libpcf/src/pin_constraints.h
index 8b3a977c0..e0ef7fe3f 100644
--- a/libopenfpga/libpcf/src/pin_constraints.h
+++ b/libopenfpga/libpcf/src/pin_constraints.h
@@ -52,6 +52,11 @@ class PinConstraints {
     /* Get the net to be constrained */
     std::string net(const PinConstraintId& pin_constraint_id) const;
 
+    /* Find the net that is constrained on a pin
+     * TODO: this function will only return the first net found in the constraint list    
+     */
+    std::string pin_net(const openfpga::BasicPort& pin) const;
+
     /* Check if there are any pin constraints */
     bool empty() const;
 
diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
index d55a59834..e861e0748 100644
--- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
@@ -135,13 +135,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
         BasicPort module_clock_pin(module_global_port.get_name(), module_global_port.pins()[pin_id], module_global_port.pins()[pin_id]);
 
         /* If the clock port name is in the pin constraints, we should wire it to the constrained pin */
-        std::string constrained_net_name;
-        for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
-          if (module_clock_pin == pin_constraints.pin(pin_constraint)) {
-            constrained_net_name = pin_constraints.net(pin_constraint); 
-            break;
-          }
-        }
+        std::string constrained_net_name = pin_constraints.pin_net(module_clock_pin);
 
         /* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */
         if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name)
@@ -179,13 +173,7 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
                                   module_global_port.pins()[pin_id]);
 
       /* If the global port name is in the pin constraints, we should wire it to the constrained pin */
-      std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET);
-      for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
-        if (module_global_pin == pin_constraints.pin(pin_constraint)) {
-          constrained_net_name = pin_constraints.net(pin_constraint); 
-          break;
-        }
-      }
+      std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
 
       /* - If constrained to a given net in the benchmark, we connect the global pin to the net
        * - If constrained to an open net in the benchmark, we assign it to a default value 
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index cc7b9fb98..7ac222ce6 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -385,13 +385,7 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
       /* Regular reset port can be mapped by a net from user design */
       if (false == fabric_global_port_info.global_port_is_prog(fabric_global_port)) {
         /* If the global port name is in the pin constraints, we should wire it to the constrained pin */
-        std::string constrained_net_name = std::string(PIN_CONSTRAINT_OPEN_NET);
-        for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
-          if (module_global_pin == pin_constraints.pin(pin_constraint)) {
-            constrained_net_name = pin_constraints.net(pin_constraint); 
-            break;
-          }
-        }
+        std::string constrained_net_name = pin_constraints.pin_net(module_global_pin);
 
         /* - If constrained to a given net in the benchmark, we connect the global pin to the net */
         if (std::string(PIN_CONSTRAINT_OPEN_NET) != constrained_net_name) {