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Merge pull request #236 from lnis-uofu/tpagarani_dev 

Tpagarani dev
This commit is contained in:
ganeshgore 2021-02-16 11:04:46 -07:00 committed by GitHub
parent 45e8baf98f 426b6449d8
commit d4ab913baa
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 6 additions and 3 deletions
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3
openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
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@ -10,7 +10,8 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base # Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options # to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges #link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist # Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

2
openfpga_flow/scripts/run_fpga_flow.py
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@ -261,6 +261,8 @@ def main():
run_ace2() run_ace2()
run_pro_blif_3arg() run_pro_blif_3arg()
run_rewrite_verilog() run_rewrite_verilog()
else:
shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
if (args.fpga_flow == "vpr_blif"): if (args.fpga_flow == "vpr_blif"):
collect_files_for_vpr() collect_files_for_vpr()
logger.info("Runing OpenFPGA Shell Engine ") logger.info("Runing OpenFPGA Shell Engine ")

4
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -9,7 +9,7 @@
[GENERAL] [GENERAL]
run_engine=openfpga_shell run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true power_analysis = false
spice_output=false spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml