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[Tool] Avoid outputting signal initialization codes because they are bulky

This commit is contained in:
tangxifan 2020-12-06 14:29:16 -07:00
parent cb2bd2e31c
commit d11a3d9fef
3 changed files with 17 additions and 12 deletions
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3
openfpga/src/fpga_verilog/verilog_api.cpp
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@ -210,8 +210,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
netlist_name, netlist_name,
top_testbench_file_path, top_testbench_file_path,
simulation_setting, simulation_setting,
options.fast_configuration(), options);
options.explicit_port_mapping());
} }
/* Generate exchangeable files which contains simulation settings */ /* Generate exchangeable files which contains simulation settings */

12
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1779,8 +1779,10 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const std::string& circuit_name, const std::string& circuit_name,
const std::string& verilog_fname, const std::string& verilog_fname,
const SimulationSetting& simulation_parameters, const SimulationSetting& simulation_parameters,
const bool& fast_configuration, const VerilogTestbenchOption& options) {
const bool& explicit_port_mapping) {
bool fast_configuration = options.fast_configuration();
bool explicit_port_mapping = options.explicit_port_mapping();
std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'"); std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
@ -1917,12 +1919,16 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
module_manager, top_module, module_manager, top_module,
bitstream_manager, fabric_bitstream); bitstream_manager, fabric_bitstream);
/* Add signal initialization */ /* Add signal initialization:
* Bypass writing codes to files due to the autogenerated codes are very large.
*/
if (true == options.include_signal_init()) {
print_verilog_testbench_signal_initialization(fp, print_verilog_testbench_signal_initialization(fp,
std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME), std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
circuit_lib, circuit_lib,
module_manager, module_manager,
top_module); top_module);
}
/* Add stimuli for reset, set, clock and iopad signals */ /* Add stimuli for reset, set, clock and iopad signals */
print_verilog_testbench_random_stimuli(fp, atom_ctx, print_verilog_testbench_random_stimuli(fp, atom_ctx,

4
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -16,6 +16,7 @@
#include "fabric_global_port_info.h" #include "fabric_global_port_info.h"
#include "vpr_netlist_annotation.h" #include "vpr_netlist_annotation.h"
#include "simulation_setting.h" #include "simulation_setting.h"
#include "verilog_testbench_options.h"
/******************************************************************** /********************************************************************
* Function declaration * Function declaration
@ -37,8 +38,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const std::string& circuit_name, const std::string& circuit_name,
const std::string& verilog_fname, const std::string& verilog_fname,
const SimulationSetting& simulation_parameters, const SimulationSetting& simulation_parameters,
const bool& fast_configuration, const VerilogTestbenchOption& options);
const bool& explicit_port_mapping);
} /* end namespace openfpga */ } /* end namespace openfpga */