diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 623f141f1..2de8b35f0 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -210,8 +210,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
                                 netlist_name,
                                 top_testbench_file_path,
                                 simulation_setting,
-                                options.fast_configuration(),
-                                options.explicit_port_mapping());
+                                options);
   }
 
   /* Generate exchangeable files which contains simulation settings */
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 581094fbd..ce21a2e65 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -1779,8 +1779,10 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
                                  const SimulationSetting& simulation_parameters,
-                                 const bool& fast_configuration,
-                                 const bool& explicit_port_mapping) {
+                                 const VerilogTestbenchOption& options) {
+
+  bool fast_configuration = options.fast_configuration();
+  bool explicit_port_mapping = options.explicit_port_mapping();
 
   std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
 
@@ -1917,12 +1919,16 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                         module_manager, top_module,
                                         bitstream_manager, fabric_bitstream);
 
-  /* Add signal initialization */
-  print_verilog_testbench_signal_initialization(fp,
-                                                std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
-                                                circuit_lib,
-                                                module_manager,
-                                                top_module);
+  /* Add signal initialization: 
+   * Bypass writing codes to files due to the autogenerated codes are very large.
+   */
+  if (true == options.include_signal_init()) {
+    print_verilog_testbench_signal_initialization(fp,
+                                                  std::string(TOP_TESTBENCH_FPGA_INSTANCE_NAME),
+                                                  circuit_lib,
+                                                  module_manager,
+                                                  top_module);
+  }
 
   /* Add stimuli for reset, set, clock and iopad signals */
   print_verilog_testbench_random_stimuli(fp, atom_ctx,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h
index 1a657c526..296900539 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h
@@ -16,6 +16,7 @@
 #include "fabric_global_port_info.h"
 #include "vpr_netlist_annotation.h"
 #include "simulation_setting.h"
+#include "verilog_testbench_options.h"
 
 /********************************************************************
  * Function declaration
@@ -37,8 +38,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const std::string& circuit_name,
                                  const std::string& verilog_fname,
                                  const SimulationSetting& simulation_parameters,
-                                 const bool& fast_configuration,
-                                 const bool& explicit_port_mapping);
+                                 const VerilogTestbenchOption& options);
 
 } /* end namespace openfpga */