adapt essential gates for submodule generation
This commit is contained in:
tangxifan
parent
2eba882332
commit
cf34339e96
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@ -0,0 +1,585 @@
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/************************************************
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* This file includes functions on
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* outputting Verilog netlists for essential gates
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* which are inverters, buffers, transmission-gates
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* logic gates etc.
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***********************************************/
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#include <fstream>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "module_manager.h"
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#include "module_manager_utils.h"
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_submodule_utils.h"
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#include "verilog_essential_gates.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/************************************************
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* Print Verilog body codes of a power-gated inverter
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* This function does NOT generate any port map !
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***********************************************/
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static
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void print_verilog_power_gated_invbuf_body(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const CircuitPortId& input_port,
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const CircuitPortId& output_port,
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const std::vector<CircuitPortId>& power_gate_ports) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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print_verilog_comment(fp, std::string("----- Verilog codes of a power-gated inverter -----"));
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/* Create a sensitive list */
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fp << "\treg " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
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fp << "\talways @(" << std::endl;
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/* Power-gate port first*/
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for (const auto& power_gate_port : power_gate_ports) {
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/* Skip first comma to dump*/
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if (0 < &power_gate_port - &power_gate_ports[0]) {
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fp << ",";
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}
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fp << circuit_lib.port_prefix(power_gate_port);
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}
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fp << circuit_lib.port_prefix(input_port) << ") begin" << std::endl;
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/* Dump the case of power-gated */
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fp << "\t\tif (";
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/* For the first pin, we skip output comma */
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size_t port_cnt = 0;
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for (const auto& power_gate_port : power_gate_ports) {
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for (const auto& power_gate_pin : circuit_lib.pins(power_gate_port)) {
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if (0 < port_cnt) {
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fp << std::endl << "\t\t&&";
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}
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fp << "(";
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/* Power-gated signal are disable during operating, enabled during configuration,
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* Therefore, we need to reverse them here
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*/
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if (0 == circuit_lib.port_default_value(power_gate_port)) {
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fp << "~";
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}
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fp << circuit_lib.port_prefix(power_gate_port) << "[" << power_gate_pin << "])";
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port_cnt++; /* Update port counter*/
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}
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}
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fp << ") begin" << std::endl;
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fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = ";
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/* Branch on the type of inverter/buffer:
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* 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages,
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* we invert the input to output
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* 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages,
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* we wire the input to output
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*/
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if ( (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model))
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|| ( (CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model))
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&& (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model))
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&& (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) {
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fp << "~";
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}
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fp << circuit_lib.port_prefix(input_port) << ";" << std::endl;
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fp << "\t\tend else begin" << std::endl;
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fp << "\t\t\tassign " << circuit_lib.port_prefix(output_port) << "_reg = 1'bz;" << std::endl;
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fp << "\t\tend" << std::endl;
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fp << "\tend" << std::endl;
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fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = " << circuit_lib.port_prefix(output_port) << "_reg;" << std::endl;
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}
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/************************************************
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* Print Verilog body codes of a regular inverter
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* This function does NOT generate any port map !
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***********************************************/
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static
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void print_verilog_invbuf_body(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const CircuitPortId& input_port,
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const CircuitPortId& output_port) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----"));
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fp << "\tassign " << circuit_lib.port_prefix(output_port) << " = (" << circuit_lib.port_prefix(input_port) << " === 1'bz)? $random : ";
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/* Branch on the type of inverter/buffer:
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* 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages,
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* we invert the input to output
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* 2. If this is a buffer or an tapere(multi-stage) buffer with even number of stages,
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* we wire the input to output
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*/
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if ( (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model))
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|| ( (CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model))
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&& (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model))
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&& (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) {
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fp << "~";
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}
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fp << circuit_lib.port_prefix(input_port) << ";" << std::endl;
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}
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/************************************************
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* Print a Verilog module of inverter or buffer
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* or tapered buffer to a file
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***********************************************/
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static
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void print_verilog_invbuf_module(ModuleManager& module_manager,
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std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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/* Find the input port, output port and global inputs*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
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/* Make sure:
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* There is only 1 input port and 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
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VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
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/* TODO: move the check codes to check_circuit_library.h */
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/* If the circuit model is power-gated, we need to find at least one global config_enable signals */
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if (true == circuit_lib.is_power_gated(circuit_model)) {
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/* Check all the ports we have are good for a power-gated circuit model */
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size_t num_err = 0;
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/* We need at least one global port */
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if (0 == global_ports.size()) {
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num_err++;
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}
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/* All the global ports should be config_enable */
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for (const auto& port : global_ports) {
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if (false == circuit_lib.port_is_config_enable(port)) {
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num_err++;
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}
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}
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/* Report errors if there are any */
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if (0 < num_err) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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}
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Finish dumping ports */
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/* Assign logics : depending on topology */
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/* Error out for unsupported technology */
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if ( ( CIRCUIT_MODEL_BUF_INV != circuit_lib.buffer_type(circuit_model))
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&& ( CIRCUIT_MODEL_BUF_BUF != circuit_lib.buffer_type(circuit_model)) ) {
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid topology for circuit model '%s'!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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if (true == circuit_lib.is_power_gated(circuit_model)) {
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/* Output Verilog codes for a power-gated inverter */
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print_verilog_power_gated_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0], global_ports);
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} else {
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/* Output Verilog codes for a regular inverter */
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print_verilog_invbuf_body(fp, circuit_lib, circuit_model, input_ports[0], output_ports[0]);
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}
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/* Print timing info */
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print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
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/* Print signal initialization */
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print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
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}
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/************************************************
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* Print a Verilog module of a pass-gate,
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* either transmission-gate or pass-transistor
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***********************************************/
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static
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void print_verilog_passgate_module(ModuleManager& module_manager,
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std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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/* Find the input port, output port*/
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std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
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switch (circuit_lib.pass_gate_logic_type(circuit_model)) {
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case CIRCUIT_MODEL_PASS_GATE_TRANSMISSION:
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/* Make sure:
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* There is only 3 input port (in, sel, selb),
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* each size of which is 1
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*/
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VTR_ASSERT( 3 == input_ports.size() );
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for (const auto& input_port : input_ports) {
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VTR_ASSERT(1 == circuit_lib.port_size(input_port));
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}
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break;
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case CIRCUIT_MODEL_PASS_GATE_TRANSISTOR:
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/* Make sure:
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* There is only 2 input port (in, sel),
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* each size of which is 1
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*/
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VTR_ASSERT( 2 == input_ports.size() );
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for (const auto& input_port : input_ports) {
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VTR_ASSERT(1 == circuit_lib.port_size(input_port));
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}
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid topology for circuit model '%s'!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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/* Make sure:
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* There is only 1 output port,
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* each size of which is 1
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*/
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VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Finish dumping ports */
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/* Dump logics: we propagate input to the output when the gate is '1'
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* the input is blocked from output when the gate is '0'
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*/
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fp << "\tassign " << circuit_lib.port_prefix(output_ports[0]) << " = ";
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fp << circuit_lib.port_prefix(input_ports[1]) << " ? " << circuit_lib.port_prefix(input_ports[0]);
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fp << " : 1'bz;" << std::endl;
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/* Print timing info */
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print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
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/* Print signal initialization */
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print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
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}
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/************************************************
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* Print Verilog body codes of an N-input AND gate
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***********************************************/
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static
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void print_verilog_and_or_gate_body(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const std::vector<CircuitPortId>& input_ports,
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const std::vector<CircuitPortId>& output_ports) {
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/* Ensure a valid file handler*/
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VTR_ASSERT(true == valid_file_stream(fp));
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/* Find the logic operator for the gate */
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std::string gate_verilog_operator;
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switch (circuit_lib.gate_type(circuit_model)) {
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case CIRCUIT_MODEL_GATE_AND:
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gate_verilog_operator = "&";
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break;
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case CIRCUIT_MODEL_GATE_OR:
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gate_verilog_operator = "|";
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid topology for circuit model '%s'!\n",
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circuit_lib.model_name(circuit_model).c_str());
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exit(1);
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}
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/* Output verilog codes */
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print_verilog_comment(fp, std::string("----- Verilog codes of a " + std::to_string(input_ports.size()) + "-input " + std::to_string(output_ports.size()) + "-output AND gate -----"));
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for (const auto& output_port : output_ports) {
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for (const auto& output_pin : circuit_lib.pins(output_port)) {
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BasicPort output_port_info(circuit_lib.port_prefix(output_port), output_pin, output_pin);
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fp << "\tassign " << generate_verilog_port(VERILOG_PORT_CONKT, output_port_info);
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fp << " = ";
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size_t port_cnt = 0;
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for (const auto& input_port : input_ports) {
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for (const auto& input_pin : circuit_lib.pins(input_port)) {
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/* Do not output AND/OR operator for the first element in the loop */
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if (0 < port_cnt) {
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fp << " " << gate_verilog_operator << " ";
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}
|
||||||
|
|
||||||
|
BasicPort input_port_info(circuit_lib.port_prefix(input_port), input_pin, input_pin);
|
||||||
|
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
|
||||||
|
|
||||||
|
/* Increment the counter for port */
|
||||||
|
port_cnt++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
fp << ";" << std::endl;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Print Verilog body codes of an 2-input MUX gate
|
||||||
|
***********************************************/
|
||||||
|
static
|
||||||
|
void print_verilog_mux2_gate_body(std::fstream& fp,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const CircuitModelId& circuit_model,
|
||||||
|
const std::vector<CircuitPortId>& input_ports,
|
||||||
|
const std::vector<CircuitPortId>& output_ports) {
|
||||||
|
/* Ensure a valid file handler*/
|
||||||
|
VTR_ASSERT(true == valid_file_stream(fp));
|
||||||
|
|
||||||
|
/* TODO: Move the check codes to check_circuit_library.cpp */
|
||||||
|
size_t num_err = 0;
|
||||||
|
/* Check on the port sequence and map */
|
||||||
|
/* MUX2 should only have 1 output port with size 1 */
|
||||||
|
if (1 != output_ports.size()) {
|
||||||
|
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||||
|
"MUX2 circuit model '%s' must have only 1 output!\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str());
|
||||||
|
num_err++;
|
||||||
|
}
|
||||||
|
for (const auto& output_port : output_ports) {
|
||||||
|
/* Bypass port size of 1 */
|
||||||
|
if (1 == circuit_lib.port_size(output_port)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||||
|
"Output port size of a MUX2 circuit model '%s' must be 1!\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str());
|
||||||
|
num_err++;
|
||||||
|
}
|
||||||
|
/* MUX2 should only have 3 output port, each of which has a port size of 1 */
|
||||||
|
if (3 != input_ports.size()) {
|
||||||
|
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||||
|
"MUX2 circuit model '%s' must have only 3 input!\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str());
|
||||||
|
num_err++;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (const auto& input_port : input_ports) {
|
||||||
|
/* Bypass port size of 1 */
|
||||||
|
if (1 == circuit_lib.port_size(input_port)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||||
|
"Input size MUX2 circuit model '%s' must be 1!\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str());
|
||||||
|
num_err++;
|
||||||
|
}
|
||||||
|
if (0 < num_err) {
|
||||||
|
exit(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Now, we output the logic of MUX2
|
||||||
|
* IMPORTANT Restriction:
|
||||||
|
* We always assum the first two inputs are data inputs
|
||||||
|
* the third input is the select port
|
||||||
|
*/
|
||||||
|
fp << "\tassign ";
|
||||||
|
BasicPort out_port_info(circuit_lib.port_prefix(output_ports[0]), 0, 0);
|
||||||
|
BasicPort sel_port_info(circuit_lib.port_prefix(input_ports[2]), 0, 0);
|
||||||
|
BasicPort in0_port_info(circuit_lib.port_prefix(input_ports[0]), 0, 0);
|
||||||
|
BasicPort in1_port_info(circuit_lib.port_prefix(input_ports[1]), 0, 0);
|
||||||
|
|
||||||
|
fp << generate_verilog_port(VERILOG_PORT_CONKT, out_port_info);
|
||||||
|
fp << " = ";
|
||||||
|
fp << generate_verilog_port(VERILOG_PORT_CONKT, sel_port_info);
|
||||||
|
fp << " ? ";
|
||||||
|
fp << generate_verilog_port(VERILOG_PORT_CONKT, in0_port_info);
|
||||||
|
fp << " : ";
|
||||||
|
fp << generate_verilog_port(VERILOG_PORT_CONKT, in1_port_info);
|
||||||
|
fp << ";" << std::endl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Print a Verilog module of a logic gate
|
||||||
|
* which are standard cells
|
||||||
|
* Supported gate types:
|
||||||
|
* 1. N-input AND
|
||||||
|
* 2. N-input OR
|
||||||
|
* 3. 2-input MUX
|
||||||
|
***********************************************/
|
||||||
|
static
|
||||||
|
void print_verilog_gate_module(ModuleManager& module_manager,
|
||||||
|
std::fstream& fp,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const CircuitModelId& circuit_model) {
|
||||||
|
/* Ensure a valid file handler*/
|
||||||
|
VTR_ASSERT(true == valid_file_stream(fp));
|
||||||
|
|
||||||
|
/* Find the input port, output port*/
|
||||||
|
std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
|
||||||
|
std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
|
||||||
|
std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
|
||||||
|
|
||||||
|
/* Make sure:
|
||||||
|
* There is only 1 output port,
|
||||||
|
* each size of which is 1
|
||||||
|
*/
|
||||||
|
VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
|
||||||
|
|
||||||
|
/* Create a Verilog Module based on the circuit model, and add to module manager */
|
||||||
|
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
|
||||||
|
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
|
||||||
|
|
||||||
|
/* dump module definition + ports */
|
||||||
|
print_verilog_module_declaration(fp, module_manager, module_id);
|
||||||
|
/* Finish dumping ports */
|
||||||
|
|
||||||
|
/* Dump logics */
|
||||||
|
switch (circuit_lib.gate_type(circuit_model)) {
|
||||||
|
case CIRCUIT_MODEL_GATE_AND:
|
||||||
|
case CIRCUIT_MODEL_GATE_OR:
|
||||||
|
print_verilog_and_or_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports);
|
||||||
|
break;
|
||||||
|
case CIRCUIT_MODEL_GATE_MUX2:
|
||||||
|
print_verilog_mux2_gate_body(fp, circuit_lib, circuit_model, input_ports, output_ports);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
VTR_LOGF_ERROR(__FILE__, __LINE__,
|
||||||
|
"Invalid topology for circuit model '%s'!\n",
|
||||||
|
circuit_lib.model_name(circuit_model).c_str());
|
||||||
|
exit(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Print timing info */
|
||||||
|
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
|
||||||
|
|
||||||
|
/* Print signal initialization */
|
||||||
|
print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
|
||||||
|
|
||||||
|
/* Put an end to the Verilog module */
|
||||||
|
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Generate the Verilog netlist for a constant generator,
|
||||||
|
* i.e., either VDD or GND
|
||||||
|
***********************************************/
|
||||||
|
static
|
||||||
|
void print_verilog_constant_generator_module(const ModuleManager& module_manager,
|
||||||
|
std::fstream& fp,
|
||||||
|
const size_t& const_value) {
|
||||||
|
/* Find the module in module manager */
|
||||||
|
std::string module_name = generate_const_value_module_name(const_value);
|
||||||
|
ModuleId const_val_module = module_manager.find_module(module_name);
|
||||||
|
VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
|
||||||
|
|
||||||
|
/* Ensure a valid file handler*/
|
||||||
|
VTR_ASSERT(true == valid_file_stream(fp));
|
||||||
|
|
||||||
|
/* dump module definition + ports */
|
||||||
|
print_verilog_module_declaration(fp, module_manager, const_val_module);
|
||||||
|
/* Finish dumping ports */
|
||||||
|
|
||||||
|
/* Find the only output*/
|
||||||
|
for (const ModulePortId& module_port_id : module_manager.module_ports(const_val_module)) {
|
||||||
|
BasicPort module_port = module_manager.module_port(const_val_module, module_port_id);
|
||||||
|
print_verilog_wire_constant_values(fp, module_port, std::vector<size_t>(1, const_value));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Put an end to the Verilog module */
|
||||||
|
print_verilog_module_end(fp, module_name);
|
||||||
|
}
|
||||||
|
|
||||||
|
/************************************************
|
||||||
|
* Generate the Verilog netlist for essential gates
|
||||||
|
* include inverters, buffers, transmission-gates,
|
||||||
|
* etc.
|
||||||
|
***********************************************/
|
||||||
|
void print_verilog_submodule_essentials(ModuleManager& module_manager,
|
||||||
|
std::vector<std::string>& netlist_names,
|
||||||
|
const std::string& verilog_dir,
|
||||||
|
const std::string& submodule_dir,
|
||||||
|
const CircuitLibrary& circuit_lib) {
|
||||||
|
/* TODO: remove .bak when this part is completed and tested */
|
||||||
|
std::string verilog_fname = submodule_dir + std::string(ESSENTIALS_VERILOG_FILE_NAME);
|
||||||
|
|
||||||
|
std::fstream fp;
|
||||||
|
|
||||||
|
/* Create the file stream */
|
||||||
|
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
|
||||||
|
/* Check if the file stream if valid or not */
|
||||||
|
check_file_stream(verilog_fname.c_str(), fp);
|
||||||
|
|
||||||
|
/* Create file */
|
||||||
|
VTR_LOG("Generating Verilog netlist '%s' for essential gates...",
|
||||||
|
verilog_fname.c_str());
|
||||||
|
|
||||||
|
print_verilog_file_header(fp, "Essential gates");
|
||||||
|
|
||||||
|
print_verilog_include_defines_preproc_file(fp, verilog_dir);
|
||||||
|
|
||||||
|
/* Print constant generators */
|
||||||
|
/* VDD */
|
||||||
|
print_verilog_constant_generator_module(module_manager, fp, 0);
|
||||||
|
/* GND */
|
||||||
|
print_verilog_constant_generator_module(module_manager, fp, 1);
|
||||||
|
|
||||||
|
for (const auto& circuit_model : circuit_lib.models()) {
|
||||||
|
/* By pass user-defined modules */
|
||||||
|
if (!circuit_lib.model_verilog_netlist(circuit_model).empty()) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
|
||||||
|
print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
|
||||||
|
print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
|
||||||
|
print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Close file handler*/
|
||||||
|
fp.close();
|
||||||
|
|
||||||
|
/* Add fname to the netlist name list */
|
||||||
|
netlist_names.push_back(verilog_fname);
|
||||||
|
|
||||||
|
VTR_LOG("Done\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
#ifndef VERILOG_ESSENTIAL_GATES_H
|
||||||
|
#define VERILOG_ESSENTIAL_GATES_H
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Include header files that are required by function declaration
|
||||||
|
*******************************************************************/
|
||||||
|
#include <string>
|
||||||
|
#include "circuit_library.h"
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Function declaration
|
||||||
|
*******************************************************************/
|
||||||
|
|
||||||
|
/* begin namespace openfpga */
|
||||||
|
namespace openfpga {
|
||||||
|
|
||||||
|
void print_verilog_submodule_essentials(ModuleManager& module_manager,
|
||||||
|
std::vector<std::string>& netlist_names,
|
||||||
|
const std::string& verilog_dir,
|
||||||
|
const std::string& submodule_dir,
|
||||||
|
const CircuitLibrary& circuit_lib);
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue