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bug fix in simulation ini GPIO width

This commit is contained in:
tangxifan 2020-07-01 13:39:12 -06:00
parent b74dde919d
commit cb2baed257
1 changed files with 1 additions and 1 deletions
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2
openfpga/src/fpga_verilog/simulation_info_writer.cpp
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@ -98,7 +98,7 @@ void print_verilog_simulation_info(const std::string& ini_fname,
for (const BasicPort& module_io_port : module_io_ports) {
total_gpio_width += module_io_port.get_width();
}
ini["SIMULATION_DECK"]["GPIO_WIDTH"] = total_gpio_width;
ini["SIMULATION_DECK"]["GPIO_WIDTH"] = std::to_string(total_gpio_width);
/* I/O direction map:
* - '0' output