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[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture

This commit is contained in:
tangxifan 2020-09-16 19:26:12 -06:00
parent 2aff461f59
commit ca1bafc688
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
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@ -55,7 +55,7 @@
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="full"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/> <pinlocations pattern="spread"/>
@ -200,7 +200,7 @@
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I" num_pins="10" equivalent="full"/> <input name="I" num_pins="10" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/> <output name="O" num_pins="4" equivalent="full"/>
<clock name="clk" num_pins="1"/> <clock name="clk" num_pins="1"/>
<!-- Describe basic logic element. <!-- Describe basic logic element.
Each basic logic element has a 4-LUT that can be optionally registered Each basic logic element has a 4-LUT that can be optionally registered