From ca1bafc6886adfc98fa2c0cba6408c1f4108c480 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 19:26:12 -0600
Subject: [PATCH] [OpenFPGA Architecture] Add full pin equivalence to full
 output crossbar architecture

---
 .../vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
index b4be8823f..16ceb2be2 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -55,7 +55,7 @@
         <site pb_type="clb"/>
       </equivalent_sites>
       <input name="I" num_pins="10" equivalent="full"/>
-      <output name="O" num_pins="4" equivalent="none"/>
+      <output name="O" num_pins="4" equivalent="full"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="spread"/>
@@ -200,7 +200,7 @@
 	   -->
     <pb_type name="clb">
       <input name="I" num_pins="10" equivalent="full"/>
-      <output name="O" num_pins="4" equivalent="none"/>
+      <output name="O" num_pins="4" equivalent="full"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  
              Each basic logic element has a 4-LUT that can be optionally registered