[test] add regression test to validate compilation of openfpga cell library files

openfpga_flow/openfpga_cell_library/Makefile

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+# 
+# OpenFPGA cell library Makefile
+# ==============================
+# 
+# Check correctness of the cell library files
+
+SHELL = bash
+PYTHON_EXEC ?= python3
+
+# Put it first so that "make" without argument is like "make help".
+export COMMENT_EXTRACT
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@${PYTHON_EXEC} -c "$$COMMENT_EXTRACT"
+
+compile_verilog:
+# This command checks the compile compatibility of Verilog files
+	for f in `cat verilog_sources.f`; do iverilog $$f; done 
+
+# Functions to extract comments from Makefiles
+define COMMENT_EXTRACT
+import re
+with open ('Makefile', 'r' ) as f:
+    matches = re.finditer('^([a-zA-Z-_]*):.*\n#(.*)', f.read(), flags=re.M)
+    for _, match in enumerate(matches, start=1):
+        header, content = match[1], match[2]
+        print(f"  {header:10} {content}")
+endef

openfpga_flow/openfpga_cell_library/verilog_sources.f

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+verilog/adder.v
+verilog/aib.v
+verilog/buf4.v
+verilog/dff.v
+verilog/dpram.v
+verilog/dpram16k.v
+verilog/dpram1k.v
+verilog/dpram8k.v
+verilog/dpram_2048x8.v
+verilog/frac_mem_32k.v
+verilog/frac_mult_16x16.v
+verilog/gpio.v
+verilog/inv.v
+verilog/latch.v
+verilog/lut6.v
+verilog/mult_32x32.v
+verilog/mult_36x36.v
+verilog/mult_8x8.v
+verilog/mux2.v
+verilog/or2.v
+verilog/spram_4x1.v
+verilog/sram.v
+verilog/tap_buf4.v