start using counter benchmark in regression tests
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tangxifan
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c87dbc4880
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@ -0,0 +1,84 @@
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/* Generated by Yosys 0.9 (git sha1 f110c953, gcc 8.4.0-1ubuntu1~18.04 -fPIC -Os) */
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module counter(clk_counter, rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] , \q_counter[6] , \q_counter[7] );
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wire _00_;
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wire _01_;
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input clk_counter;
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wire n22;
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wire n26;
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wire n30;
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wire n34;
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wire n38;
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wire n42;
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wire n46;
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wire n50;
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output \q_counter[0] ;
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reg \q_counter[0] ;
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output \q_counter[1] ;
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reg \q_counter[1] ;
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output \q_counter[2] ;
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reg \q_counter[2] ;
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output \q_counter[3] ;
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reg \q_counter[3] ;
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output \q_counter[4] ;
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reg \q_counter[4] ;
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output \q_counter[5] ;
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reg \q_counter[5] ;
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output \q_counter[6] ;
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reg \q_counter[6] ;
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output \q_counter[7] ;
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reg \q_counter[7] ;
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input rst_counter;
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[0] <= 1'b0;
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else \q_counter[0] <= n22;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[1] <= 1'b0;
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else \q_counter[1] <= n26;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[2] <= 1'b0;
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else \q_counter[2] <= n30;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[3] <= 1'b0;
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else \q_counter[3] <= n34;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[4] <= 1'b0;
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else \q_counter[4] <= n38;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[5] <= 1'b0;
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else \q_counter[5] <= n42;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[6] <= 1'b0;
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else \q_counter[6] <= n46;
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end
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always @(posedge clk_counter)
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begin
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if(rst_counter) \q_counter[7] <= 1'b0;
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else \q_counter[7] <= n50;
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end
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assign n26 = 8'h14 >> { \q_counter[0] , \q_counter[1] , rst_counter };
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assign n30 = 16'h0708 >> { \q_counter[2] , rst_counter, \q_counter[0] , \q_counter[1] };
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assign n34 = 32'd8323200 >> { \q_counter[3] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] };
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assign n38 = 64'h00007fff00008000 >> { \q_counter[4] , rst_counter, \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] };
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assign n42 = 8'h14 >> { _00_, \q_counter[5] , rst_counter };
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assign _00_ = 32'd2147483648 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] };
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assign n46 = 8'h14 >> { _01_, \q_counter[6] , rst_counter };
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assign _01_ = 64'h8000000000000000 >> { \q_counter[0] , \q_counter[1] , \q_counter[2] , \q_counter[3] , \q_counter[4] , \q_counter[5] };
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assign n50 = 16'h0708 >> { \q_counter[7] , rst_counter, _01_, \q_counter[6] };
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assign n22 = 4'h1 >> { \q_counter[0] , rst_counter };
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endmodule
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@ -0,0 +1,69 @@
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# Generated by Yosys 0.9 (git sha1 UNKNOWN, clang 7.0.0 -fPIC -Os)
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.model counter
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.inputs clk_counter rst_counter
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.outputs q_counter[0] q_counter[1] q_counter[2] q_counter[3] q_counter[4] q_counter[5] q_counter[6] q_counter[7]
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.names $false
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.names $true
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1
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.names $undef
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.names q_counter[7] rst_counter q_counter[6] $abc$3686$new_n20_ $0\q_counter[7][0:0]
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0011 1
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1000 1
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1001 1
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1010 1
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.names q_counter[4] q_counter[5] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n20_
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111111 1
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.names q_counter[6] $abc$3686$new_n20_ rst_counter $0\q_counter[6][0:0]
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010 1
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100 1
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.names q_counter[5] $abc$3686$new_n23_ rst_counter $0\q_counter[5][0:0]
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010 1
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100 1
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.names q_counter[4] q_counter[3] q_counter[2] q_counter[1] q_counter[0] $abc$3686$new_n23_
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11111 1
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.names q_counter[2] rst_counter q_counter[1] q_counter[0] $0\q_counter[2][0:0]
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0011 1
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1000 1
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1001 1
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1010 1
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.names q_counter[4] rst_counter q_counter[3] q_counter[2] q_counter[1] q_counter[0] $0\q_counter[4][0:0]
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001111 1
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100000 1
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100001 1
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100010 1
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100011 1
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100100 1
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100101 1
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100110 1
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100111 1
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101000 1
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101001 1
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101010 1
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101011 1
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101100 1
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101101 1
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101110 1
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.names q_counter[3] rst_counter q_counter[2] q_counter[1] q_counter[0] $0\q_counter[3][0:0]
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00111 1
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10000 1
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10001 1
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10010 1
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10011 1
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10100 1
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10101 1
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10110 1
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.names q_counter[1] q_counter[0] rst_counter $0\q_counter[1][0:0]
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010 1
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100 1
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.names q_counter[0] rst_counter $0\q_counter[0][0:0]
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00 1
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.latch $0\q_counter[7][0:0] q_counter[7] re clk_counter 2
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.latch $0\q_counter[6][0:0] q_counter[6] re clk_counter 2
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.latch $0\q_counter[5][0:0] q_counter[5] re clk_counter 2
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.latch $0\q_counter[4][0:0] q_counter[4] re clk_counter 2
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.latch $0\q_counter[3][0:0] q_counter[3] re clk_counter 2
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.latch $0\q_counter[2][0:0] q_counter[2] re clk_counter 2
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.latch $0\q_counter[1][0:0] q_counter[1] re clk_counter 2
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.latch $0\q_counter[0][0:0] q_counter[0] re clk_counter 2
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.end
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@ -0,0 +1,20 @@
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clk_counter 0.500000 2.000000
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rst_counter 0.492200 0.201800
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q_counter[0] 0.281800 0.563400
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q_counter[1] 0.248200 0.273600
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q_counter[2] 0.183200 0.125600
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q_counter[3] 0.097400 0.044800
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q_counter[4] 0.022600 0.007200
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q_counter[5] 0.002200 0.000800
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q_counter[6] 0.000000 0.000000
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q_counter[7] 0.000000 0.000000
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$0\q_counter[7][0:0] 0 0
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$0\q_counter[6][0:0] 0 0
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$0\q_counter[5][0:0] 0 0
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$0\q_counter[4][0:0] 0 0
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$0\q_counter[3][0:0] 0 0
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$0\q_counter[2][0:0] 0 0
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$0\q_counter[1][0:0] 0 0
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$0\q_counter[0][0:0] 0 0
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$abc$3686$new_n23_ 0 0
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$abc$3686$new_n20_ 0 0
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@ -21,12 +21,12 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench0_top = counter
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
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bench0_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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