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[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation

This commit is contained in:
tangxifan 2020-09-20 15:21:33 -06:00
parent e867e203f4
commit c6ac02d210
3 changed files with 53 additions and 10 deletions
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1
openfpga/src/fpga_spice/spice_constants.h
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@ -2,6 +2,7 @@
#define SPICE_CONSTANTS_H #define SPICE_CONSTANTS_H
/* global parameters for dumping spice netlists */ /* global parameters for dumping spice netlists */
constexpr size_t SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE = 10;
constexpr char* SPICE_NETLIST_FILE_POSTFIX = ".sp"; constexpr char* SPICE_NETLIST_FILE_POSTFIX = ".sp";

28
openfpga/src/fpga_spice/spice_subckt_writer.cpp
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@ -19,6 +19,9 @@
#include "openfpga_naming.h" #include "openfpga_naming.h"
#include "module_manager_utils.h" #include "module_manager_utils.h"
#include "spice_constants.h"
#include "spice_writer_utils.h" #include "spice_writer_utils.h"
#include "spice_subckt_writer.h" #include "spice_subckt_writer.h"
@ -370,7 +373,7 @@ void write_spice_instance_to_file(std::fstream& fp,
/* Currently we limit 10 ports per line to keep a clean netlist */ /* Currently we limit 10 ports per line to keep a clean netlist */
new_line = false; new_line = false;
if (10 == pin_cnt) { if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
pin_cnt = 0; pin_cnt = 0;
fp << std::endl; fp << std::endl;
new_line = true; new_line = true;
@ -380,6 +383,29 @@ void write_spice_instance_to_file(std::fstream& fp,
} }
} }
/* Print VDD and VSS ports
* TODO: the supply ports should be derived from module manager
*/
if (true == new_line) {
std::string port_whitespace(instance_head_line.length() - 2, ' ');
fp << "+ " << port_whitespace;
}
write_space_to_file(fp, 1);
fp << SPICE_SUBCKT_VDD_PORT_NAME;
write_space_to_file(fp, 1);
fp << SPICE_SUBCKT_GND_PORT_NAME;
pin_cnt += 2;
/* Check if we need a new line */
new_line = false;
if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
pin_cnt = 0;
fp << std::endl;
new_line = true;
fit_one_line = false;
}
/* Print module name: /* Print module name:
* if port print cannot fit one line, we create a new line for the module for a clean format * if port print cannot fit one line, we create a new line for the module for a clean format
*/ */

34
openfpga/src/fpga_spice/spice_writer_utils.cpp
View File

@ -148,7 +148,7 @@ void print_spice_subckt_definition(std::fstream& fp,
/* Currently we limit 10 ports per line to keep a clean netlist */ /* Currently we limit 10 ports per line to keep a clean netlist */
new_line = false; new_line = false;
if (10 == pin_cnt) { if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
pin_cnt = 0; pin_cnt = 0;
fp << std::endl; fp << std::endl;
new_line = true; new_line = true;
@ -159,13 +159,6 @@ void print_spice_subckt_definition(std::fstream& fp,
/* Add supply ports if specified */ /* Add supply ports if specified */
if (true == include_supply_ports) { if (true == include_supply_ports) {
/* Check if we need a new line */
new_line = false;
if (10 == pin_cnt) {
pin_cnt = 0;
fp << std::endl;
new_line = true;
}
/* Print VDD and VSS ports /* Print VDD and VSS ports
* TODO: the supply ports should be derived from module manager * TODO: the supply ports should be derived from module manager
*/ */
@ -325,7 +318,7 @@ void print_spice_subckt_instance(std::fstream& fp,
/* Currently we limit 10 ports per line to keep a clean netlist */ /* Currently we limit 10 ports per line to keep a clean netlist */
new_line = false; new_line = false;
if (10 == pin_cnt) { if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
pin_cnt = 0; pin_cnt = 0;
fp << std::endl; fp << std::endl;
new_line = true; new_line = true;
@ -335,6 +328,29 @@ void print_spice_subckt_instance(std::fstream& fp,
} }
} }
/* Print VDD and VSS ports
* TODO: the supply ports should be derived from module manager
*/
if (true == new_line) {
std::string port_whitespace(instance_head_line.length() - 2, ' ');
fp << "+ " << port_whitespace;
}
write_space_to_file(fp, 1);
fp << SPICE_SUBCKT_VDD_PORT_NAME;
write_space_to_file(fp, 1);
fp << SPICE_SUBCKT_GND_PORT_NAME;
pin_cnt += 2;
/* Check if we need a new line */
new_line = false;
if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
pin_cnt = 0;
fp << std::endl;
new_line = true;
fit_one_line = false;
}
/* Print module name: /* Print module name:
* if port print cannot fit one line, we create a new line for the module for a clean format * if port print cannot fit one line, we create a new line for the module for a clean format
*/ */