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Merge pull request #1343 from lnis-uofu/xt_default_nettype 

Now default_nettype is switched to ``wire`` by the end of each module that is generated by OpenFPGA
This commit is contained in:
tangxifan 2023-09-07 10:17:37 -07:00 committed by GitHub
parent 52710934a5 1287097ce5
commit c66db467f3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
135 changed files with 252 additions and 601 deletions
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3
.github/workflows/install_dependencies_build.sh vendored
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@ -62,4 +62,5 @@ apt-get install -y \
clang-8 \
clang-10 \
clang-format-10 \
libxml2-utils
libxml2-utils \
libssl-dev

4
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -186,7 +186,7 @@ void print_verilog_full_testbench_include_netlists(
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"),
options.time_stamp());
options.time_stamp(), true);
/* If relative path is forced, we do not include an src_dir_path in the
* netlist */
@ -248,7 +248,7 @@ void print_verilog_preconfigured_testbench_include_netlists(
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"),
options.time_stamp());
options.time_stamp(), true);
/* If relative path is forced, we do not include an src_dir_path in the
* netlist */

12
openfpga/src/fpga_verilog/verilog_decoders.cpp
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@ -96,7 +96,7 @@ static void print_verilog_mux_local_decoder_module(
std::to_string(data_size) + "-bit data -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
return;
}
@ -147,7 +147,7 @@ static void print_verilog_mux_local_decoder_module(
std::to_string(data_size) + "-bit data -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/***************************************************************************************
@ -430,7 +430,7 @@ static void print_verilog_arch_decoder_module(
std::to_string(data_size) + "-bit data -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
return;
}
@ -575,7 +575,7 @@ static void print_verilog_arch_decoder_module(
std::to_string(data_size) + "-bit data -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/***************************************************************************************
@ -693,7 +693,7 @@ static void print_verilog_arch_decoder_with_data_in_module(
std::to_string(data_size) + "-bit data -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
return;
}
@ -763,7 +763,7 @@ static void print_verilog_arch_decoder_with_data_in_module(
std::to_string(data_size) + "-bit data -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/***************************************************************************************

11
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -209,7 +209,8 @@ static void print_verilog_invbuf_module(
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
default_net_type);
}
/************************************************
@ -290,7 +291,8 @@ static void print_verilog_passgate_module(
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
default_net_type);
}
/************************************************
@ -494,7 +496,8 @@ static void print_verilog_gate_module(
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model),
default_net_type);
}
/************************************************
@ -528,7 +531,7 @@ static void print_verilog_constant_generator_module(
}
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/************************************************

3
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -364,7 +364,8 @@ void print_verilog_random_top_testbench(
/* Testbench ends*/
print_verilog_module_end(fp,
std::string(circuit_name) +
std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX));
std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX),
VERILOG_DEFAULT_NET_TYPE_WIRE);
/* Close the file stream */
fp.close();

2
openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp
View File

@ -547,7 +547,7 @@ int print_verilog_mock_fpga_wrapper(
benchmark_clock_port_names, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
/* Testbench ends*/
print_verilog_module_end(fp, title);
print_verilog_module_end(fp, title, options.default_net_type());
/* Close the file stream */
fp.close();

3
openfpga/src/fpga_verilog/verilog_module_writer.cpp
View File

@ -608,7 +608,8 @@ void write_verilog_module_to_file(
}
/* Print an end for the module */
print_verilog_module_end(fp, module_manager.module_name(module_id));
print_verilog_module_end(fp, module_manager.module_name(module_id),
default_net_type);
/* Print an empty line as splitter */
fp << std::endl;

6
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -186,7 +186,7 @@ static void print_verilog_cmos_mux_branch_module_behavioral(
fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/*********************************************************************
@ -633,7 +633,7 @@ static void generate_verilog_rram_mux_branch_module(
}
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/***********************************************
@ -1390,7 +1390,7 @@ static void generate_verilog_rram_mux_module(
module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
}
/***********************************************

6
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -654,8 +654,10 @@ int print_verilog_preconfig_top_module(
/* Testbench ends*/
print_verilog_module_end(
fp, std::string(circuit_name) +
std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX));
fp,
std::string(circuit_name) +
std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX),
options.default_net_type());
/* Close the file stream */
fp.close();

2
openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
View File

@ -174,7 +174,7 @@ static void print_one_verilog_template_module(
fp, std::string("----- Internal logic should end here -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
print_verilog_module_end(fp, module_name, default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;

6
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2675,8 +2675,10 @@ int print_verilog_full_testbench(
/* Testbench ends*/
print_verilog_module_end(
fp, std::string(circuit_name) +
std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX));
fp,
std::string(circuit_name) +
std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX),
options.default_net_type());
/* Close the file stream */
fp.close();

3
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -93,7 +93,8 @@ static void print_verilog_wire_module(
print_verilog_submodule_timing(fp, circuit_lib, wire_model);
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(wire_model));
print_verilog_module_end(fp, circuit_lib.model_name(wire_model),
default_net_type);
/* Add an empty line as a splitter */
fp << std::endl;

25
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
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@ -43,7 +43,8 @@ void print_verilog_default_net_type_declaration(
* include the description
***********************************************/
void print_verilog_file_header(std::fstream& fp, const std::string& usage,
const bool& include_time_stamp) {
const bool& include_time_stamp,
const bool& include_time_scale) {
VTR_ASSERT(true == valid_file_stream(fp));
fp << "//-------------------------------------------" << std::endl;
@ -60,9 +61,11 @@ void print_verilog_file_header(std::fstream& fp, const std::string& usage,
fp << "//-------------------------------------------" << std::endl;
fp << "//----- Time scale -----" << std::endl;
fp << "`timescale 1ns / 1ps" << std::endl;
fp << std::endl;
if (include_time_scale) {
fp << "//----- Time scale -----" << std::endl;
fp << "`timescale 1ns / 1ps" << std::endl;
fp << std::endl;
}
}
/********************************************************************
@ -338,7 +341,9 @@ void print_verilog_module_declaration(
VTR_ASSERT(true == valid_file_stream(fp));
/* Apply default net type from user's option */
print_verilog_default_net_type_declaration(fp, default_net_type);
if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
print_verilog_default_net_type_declaration(fp, default_net_type);
}
print_verilog_module_definition(fp, module_manager, module_id);
@ -470,8 +475,9 @@ void print_verilog_module_instance(
/************************************************
* Print an end line for a Verilog module
***********************************************/
void print_verilog_module_end(std::fstream& fp,
const std::string& module_name) {
void print_verilog_module_end(
std::fstream& fp, const std::string& module_name,
const e_verilog_default_net_type& default_net_type) {
VTR_ASSERT(true == valid_file_stream(fp));
fp << "endmodule" << std::endl;
@ -480,7 +486,10 @@ void print_verilog_module_end(std::fstream& fp,
fp << std::endl;
/* Reset default net type to be none */
print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_NONE);
if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) {
print_verilog_default_net_type_declaration(fp,
VERILOG_DEFAULT_NET_TYPE_WIRE);
}
}
/************************************************

7
openfpga/src/fpga_verilog/verilog_writer_utils.h
View File

@ -37,7 +37,8 @@ void print_verilog_default_net_type_declaration(
std::fstream& fp, const e_verilog_default_net_type& default_net_type);
void print_verilog_file_header(std::fstream& fp, const std::string& usage,
const bool& include_time_stamp);
const bool& include_time_stamp,
const bool& include_time_scale = false);
void print_verilog_include_netlist(std::fstream& fp,
const std::string& netlist_name);
@ -81,7 +82,9 @@ void print_verilog_module_instance(
const std::map<std::string, BasicPort>& port2port_name_map,
const bool& use_explicit_port_map);
void print_verilog_module_end(std::fstream& fp, const std::string& module_name);
void print_verilog_module_end(
std::fstream& fp, const std::string& module_name,
const e_verilog_default_net_type& default_net_type);
std::string generate_verilog_port(
const enum e_dump_verilog_port_type& dump_port_type,

6
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -121,6 +118,3 @@ end
endmodule
// ----- END Verilog module for and2_top_formal_verification_random_tb -----
//----- Default net type -----
`default_nettype none

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -498,5 +495,5 @@ endmodule
// ----- END Verilog module for and2_top_formal_verification -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include defines: preproc flags -----
`include "fpga_defines.v"

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_defines.v
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@ -4,8 +4,5 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
`define ENABLE_TIMING 1

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -456,7 +453,7 @@ endmodule
// ----- END Verilog module for fpga_top -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_clb -----
//----- Default net type -----
`default_nettype none
@ -105,7 +102,7 @@ endmodule
// ----- END Verilog module for grid_clb -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_bottom -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_bottom -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_left -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_left -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_right -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_right -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_top -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_top -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: clb -----
//----- Default net type -----
`default_nettype none
@ -420,7 +417,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_clb_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: fle -----
//----- Default net type -----
`default_nettype none
@ -102,7 +99,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: ble4 -----
//----- Default net type -----
`default_nettype none
@ -124,7 +121,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -58,7 +55,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -62,7 +59,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: io -----
//----- Default net type -----
`default_nettype none
@ -69,7 +66,7 @@ endmodule
// ----- END Verilog module for logical_tile_io_mode_io_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -65,7 +62,7 @@ endmodule
// ----- END Verilog module for logical_tile_io_mode_physical__iopad -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -363,7 +360,7 @@ endmodule
// ----- END Verilog module for cbx_1__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -363,7 +360,7 @@ endmodule
// ----- END Verilog module for cbx_1__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -344,7 +341,7 @@ endmodule
// ----- END Verilog module for cby_0__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -363,7 +360,7 @@ endmodule
// ----- END Verilog module for cby_1__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -520,7 +517,7 @@ endmodule
// ----- END Verilog module for sb_0__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -520,7 +517,7 @@ endmodule
// ----- END Verilog module for sb_0__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -520,7 +517,7 @@ endmodule
// ----- END Verilog module for sb_1__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -520,7 +517,7 @@ endmodule
// ----- END Verilog module for sb_1__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/arch_encoder.v
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@ -4,6 +4,3 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

15
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -27,7 +24,7 @@ endmodule
// ----- END Verilog module for const0 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -49,7 +46,7 @@ endmodule
// ----- END Verilog module for const1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -83,7 +80,7 @@ endmodule
// ----- END Verilog module for INVTX1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -117,7 +114,7 @@ endmodule
// ----- END Verilog module for buf4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -151,7 +148,7 @@ endmodule
// ----- END Verilog module for tap_buf4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -192,5 +189,5 @@ endmodule
// ----- END Verilog module for TGATE -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/local_encoder.v
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@ -4,6 +4,3 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -90,7 +87,7 @@ endmodule
// ----- END Verilog module for lut4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

17
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -64,7 +61,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size6_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -126,7 +123,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size4_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -182,7 +179,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size3_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -238,7 +235,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size2_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -306,7 +303,7 @@ endmodule
// ----- END Verilog module for mux_tree_size14_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -446,7 +443,7 @@ endmodule
// ----- END Verilog module for lut4_DFF_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -496,7 +493,7 @@ endmodule
// ----- END Verilog module for GPIO_DFF_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

9
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -54,7 +51,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -106,7 +103,7 @@ endmodule
// ----- END Verilog module for mux_tree_basis_input2_mem1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -158,7 +155,7 @@ endmodule
// ----- END Verilog module for lut4_mux_basis_input2_mem1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

15
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -122,7 +119,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size6 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -218,7 +215,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -302,7 +299,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size3 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -374,7 +371,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size2 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -590,7 +587,7 @@ endmodule
// ----- END Verilog module for mux_tree_size14 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -819,7 +816,7 @@ endmodule
// ----- END Verilog module for lut4_mux -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v
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@ -4,6 +4,3 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

9
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- Template Verilog module for DFFSRQ -----
//----- Default net type -----
`default_nettype none
@ -43,7 +40,7 @@ endmodule
// ----- END Verilog module for DFFSRQ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
// ----- Template Verilog module for DFF -----
@ -79,7 +76,7 @@ endmodule
// ----- END Verilog module for DFF -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
// ----- Template Verilog module for GPIO -----
@ -115,6 +112,6 @@ endmodule
// ----- END Verilog module for GPIO -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Verilog modules for regular wires -----
//----- Default net type -----
`default_nettype none
@ -33,7 +30,7 @@ endmodule
// ----- END Verilog module for direct_interc -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
// ----- END Verilog modules for regular wires -----

6
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -121,6 +118,3 @@ end
endmodule
// ----- END Verilog module for and2_top_formal_verification_random_tb -----
//----- Default net type -----
`default_nettype none

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -2528,5 +2525,5 @@ endmodule
// ----- END Verilog module for and2_top_formal_verification -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include defines: preproc flags -----
`include "fpga_defines.v"

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_defines.v
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@ -4,8 +4,5 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
`define ENABLE_TIMING 1

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -2856,7 +2853,7 @@ endmodule
// ----- END Verilog module for fpga_top -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_clb -----
//----- Default net type -----
`default_nettype none
@ -105,7 +102,7 @@ endmodule
// ----- END Verilog module for grid_clb -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_bottom -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_bottom -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_left -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_left -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_right -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_right -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_top -----
//----- Default net type -----
`default_nettype none
@ -162,7 +159,7 @@ endmodule
// ----- END Verilog module for grid_io_top -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: clb -----
//----- Default net type -----
`default_nettype none
@ -420,7 +417,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_clb_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: fle -----
//----- Default net type -----
`default_nettype none
@ -102,7 +99,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: ble4 -----
//----- Default net type -----
`default_nettype none
@ -124,7 +121,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -58,7 +55,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -62,7 +59,7 @@ endmodule
// ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Physical programmable logic block Verilog module: io -----
//----- Default net type -----
`default_nettype none
@ -69,7 +66,7 @@ endmodule
// ----- END Verilog module for logical_tile_io_mode_io_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -65,7 +62,7 @@ endmodule
// ----- END Verilog module for logical_tile_io_mode_physical__iopad -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -339,7 +336,7 @@ endmodule
// ----- END Verilog module for cbx_1__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -244,7 +241,7 @@ endmodule
// ----- END Verilog module for cbx_1__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -339,7 +336,7 @@ endmodule
// ----- END Verilog module for cbx_1__4_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -320,7 +317,7 @@ endmodule
// ----- END Verilog module for cby_0__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -225,7 +222,7 @@ endmodule
// ----- END Verilog module for cby_1__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -339,7 +336,7 @@ endmodule
// ----- END Verilog module for cby_4__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -400,7 +397,7 @@ endmodule
// ----- END Verilog module for sb_0__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -400,7 +397,7 @@ endmodule
// ----- END Verilog module for sb_0__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -400,7 +397,7 @@ endmodule
// ----- END Verilog module for sb_0__4_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -376,7 +373,7 @@ endmodule
// ----- END Verilog module for sb_1__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -390,7 +387,7 @@ endmodule
// ----- END Verilog module for sb_1__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -428,7 +425,7 @@ endmodule
// ----- END Verilog module for sb_1__4_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -400,7 +397,7 @@ endmodule
// ----- END Verilog module for sb_4__0_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -428,7 +425,7 @@ endmodule
// ----- END Verilog module for sb_4__1_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -400,7 +397,7 @@ endmodule
// ----- END Verilog module for sb_4__4_ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/arch_encoder.v
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@ -4,6 +4,3 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

15
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -27,7 +24,7 @@ endmodule
// ----- END Verilog module for const0 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -49,7 +46,7 @@ endmodule
// ----- END Verilog module for const1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -83,7 +80,7 @@ endmodule
// ----- END Verilog module for INVTX1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -117,7 +114,7 @@ endmodule
// ----- END Verilog module for buf4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -151,7 +148,7 @@ endmodule
// ----- END Verilog module for tap_buf4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
//----- Default net type -----
`default_nettype none
@ -192,5 +189,5 @@ endmodule
// ----- END Verilog module for TGATE -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/local_encoder.v
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@ -4,6 +4,3 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -90,7 +87,7 @@ endmodule
// ----- END Verilog module for lut4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

25
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -64,7 +61,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size4_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -120,7 +117,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size2_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -188,7 +185,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size10_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -256,7 +253,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size8_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -324,7 +321,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size9_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -392,7 +389,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size11_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -448,7 +445,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size3_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -510,7 +507,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size5_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -578,7 +575,7 @@ endmodule
// ----- END Verilog module for mux_tree_size14_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -718,7 +715,7 @@ endmodule
// ----- END Verilog module for lut4_DFF_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -768,7 +765,7 @@ endmodule
// ----- END Verilog module for GPIO_DFF_mem -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

9
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -54,7 +51,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -106,7 +103,7 @@ endmodule
// ----- END Verilog module for mux_tree_basis_input2_mem1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -158,7 +155,7 @@ endmodule
// ----- END Verilog module for lut4_mux_basis_input2_mem1 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

23
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -98,7 +95,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size4 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -170,7 +167,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size2 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -338,7 +335,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size10 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -482,7 +479,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size8 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -638,7 +635,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size9 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -818,7 +815,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size11 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -902,7 +899,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size3 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -1010,7 +1007,7 @@ endmodule
// ----- END Verilog module for mux_tree_tapbuf_size5 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -1226,7 +1223,7 @@ endmodule
// ----- END Verilog module for mux_tree_size14 -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
@ -1455,7 +1452,7 @@ endmodule
// ----- END Verilog module for lut4_mux -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v
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@ -4,6 +4,3 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps

9
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- Template Verilog module for DFFSRQ -----
//----- Default net type -----
`default_nettype none
@ -43,7 +40,7 @@ endmodule
// ----- END Verilog module for DFFSRQ -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
// ----- Template Verilog module for DFF -----
@ -79,7 +76,7 @@ endmodule
// ----- END Verilog module for DFF -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
// ----- Template Verilog module for GPIO -----
@ -115,6 +112,6 @@ endmodule
// ----- END Verilog module for GPIO -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v
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@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Verilog modules for regular wires -----
//----- Default net type -----
`default_nettype none
@ -33,7 +30,7 @@ endmodule
// ----- END Verilog module for direct_interc -----
//----- Default net type -----
`default_nettype none
`default_nettype wire
// ----- END Verilog modules for regular wires -----

6
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -121,6 +118,3 @@ end
endmodule
// ----- END Verilog module for and2_top_formal_verification_random_tb -----
//----- Default net type -----
`default_nettype none

5
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -1081,5 +1078,5 @@ endmodule
// ----- END Verilog module for and2_top_formal_verification -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

3
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_netlists.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include defines: preproc flags -----
`include "fpga_defines.v"

3
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_defines.v
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@ -4,8 +4,5 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
`define ENABLE_TIMING 1

5
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
//----- Default net type -----
`default_nettype none
@ -1204,7 +1201,7 @@ endmodule
// ----- END Verilog module for fpga_top -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_clb -----
//----- Default net type -----
`default_nettype none
@ -135,7 +132,7 @@ endmodule
// ----- END Verilog module for grid_clb -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_bottom -----
//----- Default net type -----
`default_nettype none
@ -173,7 +170,7 @@ endmodule
// ----- END Verilog module for grid_io_bottom -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_left -----
//----- Default net type -----
`default_nettype none
@ -173,7 +170,7 @@ endmodule
// ----- END Verilog module for grid_io_left -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

5
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v
View File

@ -4,9 +4,6 @@
// Author: Xifan TANG
// Organization: University of Utah
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ----- BEGIN Grid Verilog module: grid_io_right -----
//----- Default net type -----
`default_nettype none
@ -173,7 +170,7 @@ endmodule
// ----- END Verilog module for grid_io_right -----
//----- Default net type -----
`default_nettype none
`default_nettype wire

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