From 539bcba85127daf6d0c66bf3b2f94d25a1f40a99 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 17:23:41 -0700 Subject: [PATCH 1/9] [core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types --- openfpga/src/fpga_verilog/verilog_writer_utils.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index abfc78adb..585e7ab33 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -480,7 +480,7 @@ void print_verilog_module_end(std::fstream& fp, fp << std::endl; /* Reset default net type to be none */ - print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_NONE); + print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_WIRE); } /************************************************ From 12ac7d501aedbdb73d500c0e93e364a4dd7a928c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 17:33:43 -0700 Subject: [PATCH 2/9] [ci] update dependency requirement for openssl --- .github/workflows/install_dependencies_build.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/install_dependencies_build.sh b/.github/workflows/install_dependencies_build.sh index df33bbda9..a4ea8ef14 100755 --- a/.github/workflows/install_dependencies_build.sh +++ b/.github/workflows/install_dependencies_build.sh @@ -62,4 +62,5 @@ apt-get install -y \ clang-8 \ clang-10 \ clang-format-10 \ - libxml2-utils + libxml2-utils \ + libssl-dev From 401f8098a6e42905f4bde1e9fd31ec24d5ff84f0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 17:35:03 -0700 Subject: [PATCH 3/9] [test] update golden copies --- .../and2_formal_random_top_tb.v | 2 +- .../and2_top_formal_verification.v | 2 +- .../golden_outputs_no_time_stamp/fpga_top.v | 2 +- .../lb/grid_clb.v | 2 +- .../lb/grid_io_bottom.v | 2 +- .../lb/grid_io_left.v | 2 +- .../lb/grid_io_right.v | 2 +- .../lb/grid_io_top.v | 2 +- .../lb/logical_tile_clb_mode_clb_.v | 2 +- .../lb/logical_tile_clb_mode_default__fle.v | 2 +- ...clb_mode_default__fle_mode_n1_lut4__ble4.v | 2 +- ..._fle_mode_n1_lut4__ble4_mode_default__ff.v | 2 +- ...le_mode_n1_lut4__ble4_mode_default__lut4.v | 2 +- .../lb/logical_tile_io_mode_io_.v | 2 +- .../lb/logical_tile_io_mode_physical__iopad.v | 2 +- .../routing/cbx_1__0_.v | 2 +- .../routing/cbx_1__1_.v | 2 +- .../routing/cby_0__1_.v | 2 +- .../routing/cby_1__1_.v | 2 +- .../routing/sb_0__0_.v | 2 +- .../routing/sb_0__1_.v | 2 +- .../routing/sb_1__0_.v | 2 +- .../routing/sb_1__1_.v | 2 +- .../sub_module/inv_buf_passgate.v | 12 ++++---- .../sub_module/luts.v | 2 +- .../sub_module/memories.v | 14 ++++----- .../sub_module/mux_primitives.v | 6 ++-- .../sub_module/muxes.v | 12 ++++---- .../sub_module/user_defined_templates.v | 6 ++-- .../sub_module/wires.v | 2 +- .../and2_formal_random_top_tb.v | 2 +- .../and2_top_formal_verification.v | 2 +- .../golden_outputs_no_time_stamp/fpga_top.v | 2 +- .../lb/grid_clb.v | 2 +- .../lb/grid_io_bottom.v | 2 +- .../lb/grid_io_left.v | 2 +- .../lb/grid_io_right.v | 2 +- .../lb/grid_io_top.v | 2 +- .../lb/logical_tile_clb_mode_clb_.v | 2 +- .../lb/logical_tile_clb_mode_default__fle.v | 2 +- ...clb_mode_default__fle_mode_n1_lut4__ble4.v | 2 +- ..._fle_mode_n1_lut4__ble4_mode_default__ff.v | 2 +- ...le_mode_n1_lut4__ble4_mode_default__lut4.v | 2 +- .../lb/logical_tile_io_mode_io_.v | 2 +- .../lb/logical_tile_io_mode_physical__iopad.v | 2 +- .../routing/cbx_1__0_.v | 2 +- .../routing/cbx_1__1_.v | 2 +- .../routing/cbx_1__4_.v | 2 +- .../routing/cby_0__1_.v | 2 +- .../routing/cby_1__1_.v | 2 +- .../routing/cby_4__1_.v | 2 +- .../routing/sb_0__0_.v | 2 +- .../routing/sb_0__1_.v | 2 +- .../routing/sb_0__4_.v | 2 +- .../routing/sb_1__0_.v | 2 +- .../routing/sb_1__1_.v | 2 +- .../routing/sb_1__4_.v | 2 +- .../routing/sb_4__0_.v | 2 +- .../routing/sb_4__1_.v | 2 +- .../routing/sb_4__4_.v | 2 +- .../sub_module/inv_buf_passgate.v | 12 ++++---- .../sub_module/luts.v | 2 +- .../sub_module/memories.v | 22 +++++++------- .../sub_module/mux_primitives.v | 6 ++-- .../sub_module/muxes.v | 20 ++++++------- .../sub_module/user_defined_templates.v | 6 ++-- .../sub_module/wires.v | 2 +- .../and2_formal_random_top_tb.v | 2 +- .../and2_top_formal_verification.v | 2 +- .../golden_outputs_no_time_stamp/fpga_top.v | 2 +- .../lb/grid_clb.v | 2 +- .../lb/grid_io_bottom.v | 2 +- .../lb/grid_io_left.v | 2 +- .../lb/grid_io_right.v | 2 +- .../lb/grid_io_top.v | 2 +- .../lb/logical_tile_clb_mode_clb_.v | 2 +- .../lb/logical_tile_clb_mode_default__fle.v | 2 +- ..._mode_default__fle_mode_physical__fabric.v | 2 +- ...ode_physical__fabric_mode_default__adder.v | 2 +- ...e_mode_physical__fabric_mode_default__ff.v | 2 +- ...hysical__fabric_mode_default__frac_logic.v | 2 +- ...ault__frac_logic_mode_default__frac_lut4.v | 2 +- .../lb/logical_tile_io_mode_io_.v | 2 +- .../lb/logical_tile_io_mode_physical__iopad.v | 2 +- .../routing/cbx_1__0_.v | 2 +- .../routing/cbx_1__1_.v | 2 +- .../routing/cbx_1__2_.v | 2 +- .../routing/cby_0__1_.v | 2 +- .../routing/cby_1__1_.v | 2 +- .../routing/cby_2__1_.v | 2 +- .../routing/sb_0__0_.v | 2 +- .../routing/sb_0__1_.v | 2 +- .../routing/sb_0__2_.v | 2 +- .../routing/sb_1__0_.v | 2 +- .../routing/sb_1__1_.v | 2 +- .../routing/sb_1__2_.v | 2 +- .../routing/sb_2__0_.v | 2 +- .../routing/sb_2__1_.v | 2 +- .../routing/sb_2__2_.v | 2 +- .../sub_module/inv_buf_passgate.v | 14 ++++----- .../sub_module/luts.v | 2 +- .../sub_module/memories.v | 30 +++++++++---------- .../sub_module/mux_primitives.v | 16 +++++----- .../sub_module/muxes.v | 28 ++++++++--------- .../sub_module/user_defined_templates.v | 8 ++--- .../sub_module/wires.v | 2 +- 106 files changed, 197 insertions(+), 197 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 9445b3195..0d98d30a4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -122,5 +122,5 @@ endmodule // ----- END Verilog module for and2_top_formal_verification_random_tb ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 35b9564df..113478a97 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -498,5 +498,5 @@ endmodule // ----- END Verilog module for and2_top_formal_verification ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v index ae2ece10a..81595429e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v @@ -456,7 +456,7 @@ endmodule // ----- END Verilog module for fpga_top ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v index 0f0ce39d2..1db413a17 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -105,7 +105,7 @@ endmodule // ----- END Verilog module for grid_clb ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v index 9daf025d2..11bfb39db 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_bottom ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v index b1a194968..cb1fd187c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_left ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v index be7faf2ee..8535bef0b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_right ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v index 3d3abfb86..e798c6255 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_top ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v index 14957e35e..4b8581bb7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -420,7 +420,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_clb_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v index c95b46b6c..6c34c9713 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -102,7 +102,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v index b6d266615..02a6c9d95 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v @@ -124,7 +124,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v index 35c73e6fd..31271601f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v @@ -58,7 +58,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v index f0991a232..20f45e4f6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v @@ -62,7 +62,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v index 78f53de8e..00c85c6ab 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -69,7 +69,7 @@ endmodule // ----- END Verilog module for logical_tile_io_mode_io_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v index 4969370c8..87d180da7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -65,7 +65,7 @@ endmodule // ----- END Verilog module for logical_tile_io_mode_physical__iopad ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v index 55904c8fd..6457891a5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -363,7 +363,7 @@ endmodule // ----- END Verilog module for cbx_1__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v index 5ea4f6529..4e8920e9c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -363,7 +363,7 @@ endmodule // ----- END Verilog module for cbx_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v index a236ab04e..2aa157060 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -344,7 +344,7 @@ endmodule // ----- END Verilog module for cby_0__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v index 1a7a07037..73295a2ec 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -363,7 +363,7 @@ endmodule // ----- END Verilog module for cby_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v index 637d2788f..8dd0bdd41 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -520,7 +520,7 @@ endmodule // ----- END Verilog module for sb_0__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v index 0ab0bdca9..debeed800 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -520,7 +520,7 @@ endmodule // ----- END Verilog module for sb_0__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v index 67e38f3cd..0d2862bd8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -520,7 +520,7 @@ endmodule // ----- END Verilog module for sb_1__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v index e6c236946..81bcd5c71 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -520,7 +520,7 @@ endmodule // ----- END Verilog module for sb_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v index 43295dbf2..7f6a77bac 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -27,7 +27,7 @@ endmodule // ----- END Verilog module for const0 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -49,7 +49,7 @@ endmodule // ----- END Verilog module for const1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -83,7 +83,7 @@ endmodule // ----- END Verilog module for INVTX1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -117,7 +117,7 @@ endmodule // ----- END Verilog module for buf4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -151,7 +151,7 @@ endmodule // ----- END Verilog module for tap_buf4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -192,5 +192,5 @@ endmodule // ----- END Verilog module for TGATE ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v index ad96417b8..5ab103f69 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v @@ -90,7 +90,7 @@ endmodule // ----- END Verilog module for lut4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v index 32b44a4d4..2fd066540 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v @@ -64,7 +64,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size6_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -126,7 +126,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size4_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -182,7 +182,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size3_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -238,7 +238,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size2_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -306,7 +306,7 @@ endmodule // ----- END Verilog module for mux_tree_size14_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -446,7 +446,7 @@ endmodule // ----- END Verilog module for lut4_DFF_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -496,7 +496,7 @@ endmodule // ----- END Verilog module for GPIO_DFF_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v index c4c49b75c..2b188f3b5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -54,7 +54,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -106,7 +106,7 @@ endmodule // ----- END Verilog module for mux_tree_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -158,7 +158,7 @@ endmodule // ----- END Verilog module for lut4_mux_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v index 19734e373..1797a11f1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -122,7 +122,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size6 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -218,7 +218,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -302,7 +302,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size3 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -374,7 +374,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size2 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -590,7 +590,7 @@ endmodule // ----- END Verilog module for mux_tree_size14 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -819,7 +819,7 @@ endmodule // ----- END Verilog module for lut4_mux ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v index 6369ff51a..9150689e8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -43,7 +43,7 @@ endmodule // ----- END Verilog module for DFFSRQ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for DFF ----- @@ -79,7 +79,7 @@ endmodule // ----- END Verilog module for DFF ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for GPIO ----- @@ -115,6 +115,6 @@ endmodule // ----- END Verilog module for GPIO ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v index e8d10f4cb..cf1606882 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v @@ -33,7 +33,7 @@ endmodule // ----- END Verilog module for direct_interc ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- END Verilog modules for regular wires ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 85ed90930..d6dcb020b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -122,5 +122,5 @@ endmodule // ----- END Verilog module for and2_top_formal_verification_random_tb ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v index a696e74e4..17d9c7e47 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -2528,5 +2528,5 @@ endmodule // ----- END Verilog module for and2_top_formal_verification ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v index 994954e19..4d4878838 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v @@ -2856,7 +2856,7 @@ endmodule // ----- END Verilog module for fpga_top ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v index 0f0ce39d2..1db413a17 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -105,7 +105,7 @@ endmodule // ----- END Verilog module for grid_clb ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v index 9daf025d2..11bfb39db 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_bottom ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v index b1a194968..cb1fd187c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_left ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v index be7faf2ee..8535bef0b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_right ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v index 3d3abfb86..e798c6255 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -162,7 +162,7 @@ endmodule // ----- END Verilog module for grid_io_top ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v index 14957e35e..4b8581bb7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -420,7 +420,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_clb_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v index c95b46b6c..6c34c9713 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -102,7 +102,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v index b6d266615..02a6c9d95 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v @@ -124,7 +124,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v index 35c73e6fd..31271601f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v @@ -58,7 +58,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v index f0991a232..20f45e4f6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v @@ -62,7 +62,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v index 78f53de8e..00c85c6ab 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -69,7 +69,7 @@ endmodule // ----- END Verilog module for logical_tile_io_mode_io_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v index 4969370c8..87d180da7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -65,7 +65,7 @@ endmodule // ----- END Verilog module for logical_tile_io_mode_physical__iopad ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v index f342bbc04..9c5bea24a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -339,7 +339,7 @@ endmodule // ----- END Verilog module for cbx_1__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v index 87df1ef2e..4f01e2579 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -244,7 +244,7 @@ endmodule // ----- END Verilog module for cbx_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v index 19d0a04b5..5bdcd5aec 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v @@ -339,7 +339,7 @@ endmodule // ----- END Verilog module for cbx_1__4_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v index c27c3f325..74c5af7b7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -320,7 +320,7 @@ endmodule // ----- END Verilog module for cby_0__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v index 559ede39a..84b692190 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -225,7 +225,7 @@ endmodule // ----- END Verilog module for cby_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v index 1511d59df..3549dbbc0 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v @@ -339,7 +339,7 @@ endmodule // ----- END Verilog module for cby_4__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v index 6efac65dc..429199da8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -400,7 +400,7 @@ endmodule // ----- END Verilog module for sb_0__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v index 596cf942b..908c50b60 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -400,7 +400,7 @@ endmodule // ----- END Verilog module for sb_0__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v index d4c168609..3e14c89e7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v @@ -400,7 +400,7 @@ endmodule // ----- END Verilog module for sb_0__4_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v index f1a6323de..269fb2521 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -376,7 +376,7 @@ endmodule // ----- END Verilog module for sb_1__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v index 18ec5d548..5f1119b5b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -390,7 +390,7 @@ endmodule // ----- END Verilog module for sb_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v index e2204f210..f20a666e2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v @@ -428,7 +428,7 @@ endmodule // ----- END Verilog module for sb_1__4_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v index 0cfe9fe45..b0ac09abc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v @@ -400,7 +400,7 @@ endmodule // ----- END Verilog module for sb_4__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v index 8b646b699..9e2e80db4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v @@ -428,7 +428,7 @@ endmodule // ----- END Verilog module for sb_4__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v index 04dd2f961..0fe7d3a29 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v @@ -400,7 +400,7 @@ endmodule // ----- END Verilog module for sb_4__4_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v index 43295dbf2..7f6a77bac 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -27,7 +27,7 @@ endmodule // ----- END Verilog module for const0 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -49,7 +49,7 @@ endmodule // ----- END Verilog module for const1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -83,7 +83,7 @@ endmodule // ----- END Verilog module for INVTX1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -117,7 +117,7 @@ endmodule // ----- END Verilog module for buf4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -151,7 +151,7 @@ endmodule // ----- END Verilog module for tap_buf4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -192,5 +192,5 @@ endmodule // ----- END Verilog module for TGATE ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v index ad96417b8..5ab103f69 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v @@ -90,7 +90,7 @@ endmodule // ----- END Verilog module for lut4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v index b76593430..54e3b3cc1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v @@ -64,7 +64,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size4_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -120,7 +120,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size2_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -188,7 +188,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size10_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -256,7 +256,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size8_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -324,7 +324,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size9_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -392,7 +392,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size11_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -448,7 +448,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size3_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -510,7 +510,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size5_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -578,7 +578,7 @@ endmodule // ----- END Verilog module for mux_tree_size14_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -718,7 +718,7 @@ endmodule // ----- END Verilog module for lut4_DFF_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -768,7 +768,7 @@ endmodule // ----- END Verilog module for GPIO_DFF_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v index c4c49b75c..2b188f3b5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -54,7 +54,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -106,7 +106,7 @@ endmodule // ----- END Verilog module for mux_tree_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -158,7 +158,7 @@ endmodule // ----- END Verilog module for lut4_mux_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v index f01fda941..7ef6296ef 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -98,7 +98,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -170,7 +170,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size2 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -338,7 +338,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size10 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -482,7 +482,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size8 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -638,7 +638,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size9 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -818,7 +818,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size11 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -902,7 +902,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size3 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1010,7 +1010,7 @@ endmodule // ----- END Verilog module for mux_tree_tapbuf_size5 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1226,7 +1226,7 @@ endmodule // ----- END Verilog module for mux_tree_size14 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1455,7 +1455,7 @@ endmodule // ----- END Verilog module for lut4_mux ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v index 6369ff51a..9150689e8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -43,7 +43,7 @@ endmodule // ----- END Verilog module for DFFSRQ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for DFF ----- @@ -79,7 +79,7 @@ endmodule // ----- END Verilog module for DFF ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for GPIO ----- @@ -115,6 +115,6 @@ endmodule // ----- END Verilog module for GPIO ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v index e8d10f4cb..cf1606882 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v @@ -33,7 +33,7 @@ endmodule // ----- END Verilog module for direct_interc ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- END Verilog modules for regular wires ----- diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 59580560b..4edf9b5bd 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -122,5 +122,5 @@ endmodule // ----- END Verilog module for and2_top_formal_verification_random_tb ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 5df277771..59666edf6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -1081,5 +1081,5 @@ endmodule // ----- END Verilog module for and2_top_formal_verification ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v index 17b3b18eb..50e97ba42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v @@ -1204,7 +1204,7 @@ endmodule // ----- END Verilog module for fpga_top ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v index bd9ef8b40..9e502ce3f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -135,7 +135,7 @@ endmodule // ----- END Verilog module for grid_clb ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v index 67861dfce..43c1257fa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -173,7 +173,7 @@ endmodule // ----- END Verilog module for grid_io_bottom ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v index 3345b4f7d..2fd852d32 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -173,7 +173,7 @@ endmodule // ----- END Verilog module for grid_io_left ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v index da0ee973c..6df512d13 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -173,7 +173,7 @@ endmodule // ----- END Verilog module for grid_io_right ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v index bba19d207..eed2bb988 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -173,7 +173,7 @@ endmodule // ----- END Verilog module for grid_io_top ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v index 3f8eabbf2..810ca388b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -503,7 +503,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_clb_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v index 95d5108b0..19ab0d7c6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -130,7 +130,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index e2b7e1506..14f60baf9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -227,7 +227,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v index e654f1292..a3cab551a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v @@ -57,7 +57,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v index 8f307bdae..a506f5e39 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -58,7 +58,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v index cca650256..6aa162865 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -103,7 +103,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v index 95045b56b..a4c3e635a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -75,7 +75,7 @@ endmodule // ----- END Verilog module for logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v index 6acfb4f85..8aba826c3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -73,7 +73,7 @@ endmodule // ----- END Verilog module for logical_tile_io_mode_io_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v index 4f5a6abc9..9b05fb79c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -69,7 +69,7 @@ endmodule // ----- END Verilog module for logical_tile_io_mode_physical__iopad ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v index 5c5af143c..6127be759 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -413,7 +413,7 @@ endmodule // ----- END Verilog module for cbx_1__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v index ec14dd475..b62ba05ce 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -253,7 +253,7 @@ endmodule // ----- END Verilog module for cbx_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v index fbc5293ce..76ecb10ca 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v @@ -293,7 +293,7 @@ endmodule // ----- END Verilog module for cbx_1__2_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v index bff2ca487..f852c3062 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -313,7 +313,7 @@ endmodule // ----- END Verilog module for cby_0__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v index 33b05f406..fb4501a60 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -273,7 +273,7 @@ endmodule // ----- END Verilog module for cby_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v index 6efa1d6c9..9adf53ace 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v @@ -413,7 +413,7 @@ endmodule // ----- END Verilog module for cby_2__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v index 8ec9d7006..743d6f63b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -427,7 +427,7 @@ endmodule // ----- END Verilog module for sb_0__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v index 9a834ca11..5e870301b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -404,7 +404,7 @@ endmodule // ----- END Verilog module for sb_0__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v index f1e1e7265..a7eb6d355 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v @@ -389,7 +389,7 @@ endmodule // ----- END Verilog module for sb_0__2_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v index 3721a68ab..5d038999f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -441,7 +441,7 @@ endmodule // ----- END Verilog module for sb_1__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v index d6fbaaaa4..3140d461b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -429,7 +429,7 @@ endmodule // ----- END Verilog module for sb_1__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v index 976065c42..49ccccb5a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v @@ -408,7 +408,7 @@ endmodule // ----- END Verilog module for sb_1__2_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v index 7008bfcf2..7f558fb29 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v @@ -465,7 +465,7 @@ endmodule // ----- END Verilog module for sb_2__0_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v index 87f5a67c0..ecb4a2050 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v @@ -428,7 +428,7 @@ endmodule // ----- END Verilog module for sb_2__1_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v index f38efe8e5..55c1736cb 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v @@ -427,7 +427,7 @@ endmodule // ----- END Verilog module for sb_2__2_ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v index 540526b3f..ae2d007db 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -27,7 +27,7 @@ endmodule // ----- END Verilog module for const0 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -49,7 +49,7 @@ endmodule // ----- END Verilog module for const1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -83,7 +83,7 @@ endmodule // ----- END Verilog module for INVTX1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -117,7 +117,7 @@ endmodule // ----- END Verilog module for buf4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -151,7 +151,7 @@ endmodule // ----- END Verilog module for tap_buf4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -189,7 +189,7 @@ endmodule // ----- END Verilog module for OR2 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire //----- Default net type ----- `default_nettype none @@ -230,5 +230,5 @@ endmodule // ----- END Verilog module for TGATE ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v index 5863a72d9..e455b5ef9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v @@ -107,7 +107,7 @@ endmodule // ----- END Verilog module for frac_lut4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v index 1ec1b78f4..86179510a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v @@ -91,7 +91,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size4_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -152,7 +152,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size2_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -213,7 +213,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size3_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -316,7 +316,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size11_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -419,7 +419,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size9_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -522,7 +522,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size10_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -625,7 +625,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size13_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -714,7 +714,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size7_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -803,7 +803,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size8_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -892,7 +892,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size5_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1009,7 +1009,7 @@ endmodule // ----- END Verilog module for mux_2level_size20_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1084,7 +1084,7 @@ endmodule // ----- END Verilog module for mux_1level_tapbuf_size3_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1152,7 +1152,7 @@ endmodule // ----- END Verilog module for mux_1level_tapbuf_size2_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1318,7 +1318,7 @@ endmodule // ----- END Verilog module for frac_lut4_DFFR_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1372,7 +1372,7 @@ endmodule // ----- END Verilog module for GPIO_DFFR_mem ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v index c0d3a0406..7ff534696 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -60,7 +60,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_basis_input3_mem3 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -112,7 +112,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -176,7 +176,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_basis_input4_mem4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -228,7 +228,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_basis_input2_mem2 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -298,7 +298,7 @@ endmodule // ----- END Verilog module for mux_2level_basis_input5_mem5 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -362,7 +362,7 @@ endmodule // ----- END Verilog module for mux_1level_tapbuf_basis_input4_mem4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -420,7 +420,7 @@ endmodule // ----- END Verilog module for mux_1level_tapbuf_basis_input3_mem3 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -472,7 +472,7 @@ endmodule // ----- END Verilog module for frac_lut4_mux_basis_input2_mem1 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v index 9e5b58987..e974fdc63 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -84,7 +84,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size4 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -156,7 +156,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size2 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -240,7 +240,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size3 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -371,7 +371,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size11 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -485,7 +485,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size9 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -611,7 +611,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size10 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -759,7 +759,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size13 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -870,7 +870,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size7 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -986,7 +986,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size8 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1080,7 +1080,7 @@ endmodule // ----- END Verilog module for mux_2level_tapbuf_size5 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1263,7 +1263,7 @@ endmodule // ----- END Verilog module for mux_2level_size20 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1333,7 +1333,7 @@ endmodule // ----- END Verilog module for mux_1level_tapbuf_size3 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1398,7 +1398,7 @@ endmodule // ----- END Verilog module for mux_1level_tapbuf_size2 ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire @@ -1658,7 +1658,7 @@ endmodule // ----- END Verilog module for frac_lut4_mux ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v index 861215cd6..173c18752 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -43,7 +43,7 @@ endmodule // ----- END Verilog module for DFFSRQ ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for DFFR ----- @@ -82,7 +82,7 @@ endmodule // ----- END Verilog module for DFFR ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for GPIO ----- @@ -118,7 +118,7 @@ endmodule // ----- END Verilog module for GPIO ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- Template Verilog module for ADDF ----- @@ -157,6 +157,6 @@ endmodule // ----- END Verilog module for ADDF ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v index e8d10f4cb..cf1606882 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v @@ -33,7 +33,7 @@ endmodule // ----- END Verilog module for direct_interc ----- //----- Default net type ----- -`default_nettype none +`default_nettype wire // ----- END Verilog modules for regular wires ----- From f8b2eec98836173ac3bfb2b09f64eb7900e2483c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:27:51 -0700 Subject: [PATCH 4/9] [core] now default net type wire will not appear. timescale does not show in fabric netlists --- .../verilog_auxiliary_netlists.cpp | 4 +-- .../src/fpga_verilog/verilog_decoders.cpp | 12 ++++----- .../fpga_verilog/verilog_essential_gates.cpp | 8 +++--- .../verilog_formal_random_top_testbench.cpp | 4 ++- .../verilog_mock_fpga_wrapper.cpp | 2 +- .../fpga_verilog/verilog_module_writer.cpp | 2 +- openfpga/src/fpga_verilog/verilog_mux.cpp | 6 ++--- .../verilog_preconfig_top_module.cpp | 3 ++- .../fpga_verilog/verilog_submodule_utils.cpp | 2 +- .../fpga_verilog/verilog_top_testbench.cpp | 3 ++- openfpga/src/fpga_verilog/verilog_wire.cpp | 2 +- .../src/fpga_verilog/verilog_writer_utils.cpp | 25 +++++++++++++------ .../src/fpga_verilog/verilog_writer_utils.h | 5 ++-- 13 files changed, 46 insertions(+), 32 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index 8501ac6aa..300351203 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -186,7 +186,7 @@ void print_verilog_full_testbench_include_netlists( /* Print the title */ print_verilog_file_header(fp, std::string("Netlist Summary"), - options.time_stamp()); + options.time_stamp(), true); /* If relative path is forced, we do not include an src_dir_path in the * netlist */ @@ -248,7 +248,7 @@ void print_verilog_preconfigured_testbench_include_netlists( /* Print the title */ print_verilog_file_header(fp, std::string("Netlist Summary"), - options.time_stamp()); + options.time_stamp(), true); /* If relative path is forced, we do not include an src_dir_path in the * netlist */ diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp index 73c59fed4..693384e39 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.cpp +++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp @@ -96,7 +96,7 @@ static void print_verilog_mux_local_decoder_module( std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); return; } @@ -147,7 +147,7 @@ static void print_verilog_mux_local_decoder_module( std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /*************************************************************************************** @@ -430,7 +430,7 @@ static void print_verilog_arch_decoder_module( std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); return; } @@ -575,7 +575,7 @@ static void print_verilog_arch_decoder_module( std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /*************************************************************************************** @@ -693,7 +693,7 @@ static void print_verilog_arch_decoder_with_data_in_module( std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); return; } @@ -763,7 +763,7 @@ static void print_verilog_arch_decoder_with_data_in_module( std::to_string(data_size) + "-bit data -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /*************************************************************************************** diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index 98b32bd8e..fce1ae4b9 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -209,7 +209,7 @@ static void print_verilog_invbuf_module( print_verilog_submodule_timing(fp, circuit_lib, circuit_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type); } /************************************************ @@ -290,7 +290,7 @@ static void print_verilog_passgate_module( print_verilog_submodule_timing(fp, circuit_lib, circuit_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type); } /************************************************ @@ -494,7 +494,7 @@ static void print_verilog_gate_module( print_verilog_submodule_timing(fp, circuit_lib, circuit_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model)); + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type); } /************************************************ @@ -528,7 +528,7 @@ static void print_verilog_constant_generator_module( } /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /************************************************ diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 629d1759b..9d7ec498f 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -364,7 +364,9 @@ void print_verilog_random_top_testbench( /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + - std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX)); + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX), + VERILOG_DEFAULT_NET_TYPE_WIRE + ); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp index 018ab3d77..e20f02e96 100644 --- a/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp +++ b/openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp @@ -547,7 +547,7 @@ int print_verilog_mock_fpga_wrapper( benchmark_clock_port_names, (size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE); /* Testbench ends*/ - print_verilog_module_end(fp, title); + print_verilog_module_end(fp, title, options.default_net_type()); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 4a0ede484..251d9b063 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -608,7 +608,7 @@ void write_verilog_module_to_file( } /* Print an end for the module */ - print_verilog_module_end(fp, module_manager.module_name(module_id)); + print_verilog_module_end(fp, module_manager.module_name(module_id), default_net_type); /* Print an empty line as splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index ea1d666ba..40df031e0 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -186,7 +186,7 @@ static void print_verilog_cmos_mux_branch_module_behavioral( fp, input_port, output_port, mem_port, mux_graph, mem_default_val[0]); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /********************************************************************* @@ -633,7 +633,7 @@ static void generate_verilog_rram_mux_branch_module( } /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /*********************************************** @@ -1390,7 +1390,7 @@ static void generate_verilog_rram_mux_module( module_manager, circuit_lib, fp, module_id, circuit_model, mux_graph); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); } /*********************************************** diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 18e6c5e2d..3bb7b2086 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -655,7 +655,8 @@ int print_verilog_preconfig_top_module( /* Testbench ends*/ print_verilog_module_end( fp, std::string(circuit_name) + - std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)); + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX), + VERILOG_DEFAULT_NET_TYPE_WIRE); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp index 362cd3dd2..c4877a903 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp @@ -174,7 +174,7 @@ static void print_one_verilog_template_module( fp, std::string("----- Internal logic should end here -----")); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, module_name); + print_verilog_module_end(fp, module_name, default_net_type); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index a1c16baf5..2fb8e1850 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -2676,7 +2676,8 @@ int print_verilog_full_testbench( /* Testbench ends*/ print_verilog_module_end( fp, std::string(circuit_name) + - std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX)); + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX), + VERILOG_DEFAULT_NET_TYPE_WIRE); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp index 5df8bb840..e944ae8bb 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.cpp +++ b/openfpga/src/fpga_verilog/verilog_wire.cpp @@ -93,7 +93,7 @@ static void print_verilog_wire_module( print_verilog_submodule_timing(fp, circuit_lib, wire_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(wire_model)); + print_verilog_module_end(fp, circuit_lib.model_name(wire_model), default_net_type); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index 585e7ab33..2ab0888ea 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -32,9 +32,13 @@ void print_verilog_default_net_type_declaration( std::fstream& fp, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); - fp << "//----- Default net type -----" << std::endl; - fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] + if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { + fp << "//----- Default net type -----" << std::endl; + fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; + } else { + fp << "//----- Assume default net type to be " << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] << "-----" << std::endl; + } fp << std::endl; } @@ -43,7 +47,8 @@ void print_verilog_default_net_type_declaration( * include the description ***********************************************/ void print_verilog_file_header(std::fstream& fp, const std::string& usage, - const bool& include_time_stamp) { + const bool& include_time_stamp, + const bool& include_time_scale) { VTR_ASSERT(true == valid_file_stream(fp)); fp << "//-------------------------------------------" << std::endl; @@ -60,9 +65,11 @@ void print_verilog_file_header(std::fstream& fp, const std::string& usage, fp << "//-------------------------------------------" << std::endl; - fp << "//----- Time scale -----" << std::endl; - fp << "`timescale 1ns / 1ps" << std::endl; - fp << std::endl; + if (include_time_scale) { + fp << "//----- Time scale -----" << std::endl; + fp << "`timescale 1ns / 1ps" << std::endl; + fp << std::endl; + } } /******************************************************************** @@ -471,7 +478,7 @@ void print_verilog_module_instance( * Print an end line for a Verilog module ***********************************************/ void print_verilog_module_end(std::fstream& fp, - const std::string& module_name) { + const std::string& module_name, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); fp << "endmodule" << std::endl; @@ -480,7 +487,9 @@ void print_verilog_module_end(std::fstream& fp, fp << std::endl; /* Reset default net type to be none */ - print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_WIRE); + if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { + print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_WIRE); + } } /************************************************ diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index cf9faa6b9..5a7cfd040 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -37,7 +37,8 @@ void print_verilog_default_net_type_declaration( std::fstream& fp, const e_verilog_default_net_type& default_net_type); void print_verilog_file_header(std::fstream& fp, const std::string& usage, - const bool& include_time_stamp); + const bool& include_time_stamp, + const bool& include_time_scale = false); void print_verilog_include_netlist(std::fstream& fp, const std::string& netlist_name); @@ -81,7 +82,7 @@ void print_verilog_module_instance( const std::map& port2port_name_map, const bool& use_explicit_port_map); -void print_verilog_module_end(std::fstream& fp, const std::string& module_name); +void print_verilog_module_end(std::fstream& fp, const std::string& module_name, const e_verilog_default_net_type& default_net_type); std::string generate_verilog_port( const enum e_dump_verilog_port_type& dump_port_type, From f5449530851092ac6be56d1b3ae82b0a6467a6e0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:29:30 -0700 Subject: [PATCH 5/9] [core] code format --- .../src/fpga_verilog/verilog_essential_gates.cpp | 9 ++++++--- .../verilog_formal_random_top_testbench.cpp | 3 +-- .../src/fpga_verilog/verilog_module_writer.cpp | 3 ++- .../verilog_preconfig_top_module.cpp | 7 ++++--- .../src/fpga_verilog/verilog_top_testbench.cpp | 7 ++++--- openfpga/src/fpga_verilog/verilog_wire.cpp | 3 ++- .../src/fpga_verilog/verilog_writer_utils.cpp | 16 ++++++++++------ openfpga/src/fpga_verilog/verilog_writer_utils.h | 4 +++- 8 files changed, 32 insertions(+), 20 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index fce1ae4b9..84d2e7d6c 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -209,7 +209,8 @@ static void print_verilog_invbuf_module( print_verilog_submodule_timing(fp, circuit_lib, circuit_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type); + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), + default_net_type); } /************************************************ @@ -290,7 +291,8 @@ static void print_verilog_passgate_module( print_verilog_submodule_timing(fp, circuit_lib, circuit_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type); + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), + default_net_type); } /************************************************ @@ -494,7 +496,8 @@ static void print_verilog_gate_module( print_verilog_submodule_timing(fp, circuit_lib, circuit_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), default_net_type); + print_verilog_module_end(fp, circuit_lib.model_name(circuit_model), + default_net_type); } /************************************************ diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 9d7ec498f..045a69024 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -365,8 +365,7 @@ void print_verilog_random_top_testbench( print_verilog_module_end(fp, std::string(circuit_name) + std::string(FORMAL_RANDOM_TOP_TESTBENCH_POSTFIX), - VERILOG_DEFAULT_NET_TYPE_WIRE - ); + VERILOG_DEFAULT_NET_TYPE_WIRE); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 251d9b063..af901e592 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -608,7 +608,8 @@ void write_verilog_module_to_file( } /* Print an end for the module */ - print_verilog_module_end(fp, module_manager.module_name(module_id), default_net_type); + print_verilog_module_end(fp, module_manager.module_name(module_id), + default_net_type); /* Print an empty line as splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 3bb7b2086..550ba2d63 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -654,9 +654,10 @@ int print_verilog_preconfig_top_module( /* Testbench ends*/ print_verilog_module_end( - fp, std::string(circuit_name) + - std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX), - VERILOG_DEFAULT_NET_TYPE_WIRE); + fp, + std::string(circuit_name) + + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX), + VERILOG_DEFAULT_NET_TYPE_WIRE); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 2fb8e1850..f7dd1b997 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -2675,9 +2675,10 @@ int print_verilog_full_testbench( /* Testbench ends*/ print_verilog_module_end( - fp, std::string(circuit_name) + - std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX), - VERILOG_DEFAULT_NET_TYPE_WIRE); + fp, + std::string(circuit_name) + + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX), + VERILOG_DEFAULT_NET_TYPE_WIRE); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp index e944ae8bb..544c3b7c9 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.cpp +++ b/openfpga/src/fpga_verilog/verilog_wire.cpp @@ -93,7 +93,8 @@ static void print_verilog_wire_module( print_verilog_submodule_timing(fp, circuit_lib, wire_model); /* Put an end to the Verilog module */ - print_verilog_module_end(fp, circuit_lib.model_name(wire_model), default_net_type); + print_verilog_module_end(fp, circuit_lib.model_name(wire_model), + default_net_type); /* Add an empty line as a splitter */ fp << std::endl; diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index 2ab0888ea..a6dc76e8a 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -34,10 +34,12 @@ void print_verilog_default_net_type_declaration( if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { fp << "//----- Default net type -----" << std::endl; - fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] - << std::endl; + fp << "`default_nettype " + << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; } else { - fp << "//----- Assume default net type to be " << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] << "-----" << std::endl; + fp << "//----- Assume default net type to be " + << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] + << "-----" << std::endl; } fp << std::endl; } @@ -477,8 +479,9 @@ void print_verilog_module_instance( /************************************************ * Print an end line for a Verilog module ***********************************************/ -void print_verilog_module_end(std::fstream& fp, - const std::string& module_name, const e_verilog_default_net_type& default_net_type) { +void print_verilog_module_end( + std::fstream& fp, const std::string& module_name, + const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); fp << "endmodule" << std::endl; @@ -488,7 +491,8 @@ void print_verilog_module_end(std::fstream& fp, /* Reset default net type to be none */ if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { - print_verilog_default_net_type_declaration(fp, VERILOG_DEFAULT_NET_TYPE_WIRE); + print_verilog_default_net_type_declaration(fp, + VERILOG_DEFAULT_NET_TYPE_WIRE); } } diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 5a7cfd040..665f191a2 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -82,7 +82,9 @@ void print_verilog_module_instance( const std::map& port2port_name_map, const bool& use_explicit_port_map); -void print_verilog_module_end(std::fstream& fp, const std::string& module_name, const e_verilog_default_net_type& default_net_type); +void print_verilog_module_end( + std::fstream& fp, const std::string& module_name, + const e_verilog_default_net_type& default_net_type); std::string generate_verilog_port( const enum e_dump_verilog_port_type& dump_port_type, From 2fee56548baa499054b32d1259ca7acaadcacb5b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:39:59 -0700 Subject: [PATCH 6/9] [core] fixed some bugs --- .../src/fpga_verilog/verilog_writer_utils.cpp | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index a6dc76e8a..64e8e8aac 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -32,15 +32,9 @@ void print_verilog_default_net_type_declaration( std::fstream& fp, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); - if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { - fp << "//----- Default net type -----" << std::endl; - fp << "`default_nettype " - << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; - } else { - fp << "//----- Assume default net type to be " - << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] - << "-----" << std::endl; - } + fp << "//----- Default net type -----" << std::endl; + fp << "`default_nettype " + << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; fp << std::endl; } @@ -347,7 +341,9 @@ void print_verilog_module_declaration( VTR_ASSERT(true == valid_file_stream(fp)); /* Apply default net type from user's option */ - print_verilog_default_net_type_declaration(fp, default_net_type); + if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { + print_verilog_default_net_type_declaration(fp, default_net_type); + } print_verilog_module_definition(fp, module_manager, module_id); From bcb82d43af2ff1a33d982870aeb28d7bc1dfd1ee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:40:59 -0700 Subject: [PATCH 7/9] [core] code format --- openfpga/src/fpga_verilog/verilog_writer_utils.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index 64e8e8aac..dd95205de 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -33,8 +33,8 @@ void print_verilog_default_net_type_declaration( VTR_ASSERT(true == valid_file_stream(fp)); fp << "//----- Default net type -----" << std::endl; - fp << "`default_nettype " - << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; + fp << "`default_nettype " << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] + << std::endl; fp << std::endl; } @@ -343,7 +343,7 @@ void print_verilog_module_declaration( /* Apply default net type from user's option */ if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { print_verilog_default_net_type_declaration(fp, default_net_type); - } + } print_verilog_module_definition(fp, module_manager, module_id); From eaadff34488df158b3e8d41e1bd9b2ef37c0e319 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:49:56 -0700 Subject: [PATCH 8/9] [core] fixed some bugs --- openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 2 +- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 550ba2d63..0fa26c73f 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -657,7 +657,7 @@ int print_verilog_preconfig_top_module( fp, std::string(circuit_name) + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX), - VERILOG_DEFAULT_NET_TYPE_WIRE); + options.default_net_type()); /* Close the file stream */ fp.close(); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index f7dd1b997..a0993d079 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -2678,7 +2678,7 @@ int print_verilog_full_testbench( fp, std::string(circuit_name) + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX), - VERILOG_DEFAULT_NET_TYPE_WIRE); + options.default_net_type()); /* Close the file stream */ fp.close(); From 1287097ce580edd84adeda2863c31efaa8edbc2f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:51:38 -0700 Subject: [PATCH 9/9] [test] update golden netlists --- .../and2_formal_random_top_tb.v | 6 ------ .../and2_top_formal_verification.v | 3 --- .../golden_outputs_no_time_stamp/fabric_netlists.v | 3 --- .../device_1x1/golden_outputs_no_time_stamp/fpga_defines.v | 3 --- .../device_1x1/golden_outputs_no_time_stamp/fpga_top.v | 3 --- .../device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_bottom.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_left.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_right.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_top.v | 3 --- .../lb/logical_tile_clb_mode_clb_.v | 3 --- .../lb/logical_tile_clb_mode_default__fle.v | 3 --- .../logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v | 3 --- ..._mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v | 3 --- ...ode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v | 3 --- .../lb/logical_tile_io_mode_io_.v | 3 --- .../lb/logical_tile_io_mode_physical__iopad.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_0__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/arch_encoder.v | 3 --- .../sub_module/inv_buf_passgate.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/local_encoder.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/luts.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/memories.v | 3 --- .../sub_module/mux_primitives.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/muxes.v | 3 --- .../sub_module/shift_register_banks.v | 3 --- .../sub_module/user_defined_templates.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/wires.v | 3 --- .../and2_formal_random_top_tb.v | 6 ------ .../and2_top_formal_verification.v | 3 --- .../golden_outputs_no_time_stamp/fabric_netlists.v | 3 --- .../device_4x4/golden_outputs_no_time_stamp/fpga_defines.v | 3 --- .../device_4x4/golden_outputs_no_time_stamp/fpga_top.v | 3 --- .../device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_bottom.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_left.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_right.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_top.v | 3 --- .../lb/logical_tile_clb_mode_clb_.v | 3 --- .../lb/logical_tile_clb_mode_default__fle.v | 3 --- .../logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v | 3 --- ..._mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v | 3 --- ...ode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v | 3 --- .../lb/logical_tile_io_mode_io_.v | 3 --- .../lb/logical_tile_io_mode_physical__iopad.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__4_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_0__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_4__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__4_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__4_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_4__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_4__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_4__4_.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/arch_encoder.v | 3 --- .../sub_module/inv_buf_passgate.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/local_encoder.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/luts.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/memories.v | 3 --- .../sub_module/mux_primitives.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/muxes.v | 3 --- .../sub_module/shift_register_banks.v | 3 --- .../sub_module/user_defined_templates.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/wires.v | 3 --- .../and2_formal_random_top_tb.v | 6 ------ .../and2_top_formal_verification.v | 3 --- .../golden_outputs_no_time_stamp/fabric_netlists.v | 3 --- .../golden_outputs_no_time_stamp/fpga_defines.v | 3 --- .../no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_clb.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_bottom.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_left.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_right.v | 3 --- .../golden_outputs_no_time_stamp/lb/grid_io_top.v | 3 --- .../lb/logical_tile_clb_mode_clb_.v | 3 --- .../lb/logical_tile_clb_mode_default__fle.v | 3 --- ...gical_tile_clb_mode_default__fle_mode_physical__fabric.v | 3 --- ...default__fle_mode_physical__fabric_mode_default__adder.v | 3 --- ...de_default__fle_mode_physical__fabric_mode_default__ff.v | 3 --- ...lt__fle_mode_physical__fabric_mode_default__frac_logic.v | 3 --- ...abric_mode_default__frac_logic_mode_default__frac_lut4.v | 3 --- .../lb/logical_tile_io_mode_io_.v | 3 --- .../lb/logical_tile_io_mode_physical__iopad.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cbx_1__2_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_0__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/cby_2__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_0__2_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_1__2_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_2__0_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_2__1_.v | 3 --- .../golden_outputs_no_time_stamp/routing/sb_2__2_.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/arch_encoder.v | 3 --- .../sub_module/inv_buf_passgate.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/local_encoder.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/luts.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/memories.v | 3 --- .../sub_module/mux_primitives.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/muxes.v | 3 --- .../sub_module/shift_register_banks.v | 3 --- .../sub_module/user_defined_templates.v | 3 --- .../golden_outputs_no_time_stamp/sub_module/wires.v | 3 --- 121 files changed, 372 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 0d98d30a4..c0daea5f7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none @@ -121,6 +118,3 @@ end endmodule // ----- END Verilog module for and2_top_formal_verification_random_tb ----- -//----- Default net type ----- -`default_nettype wire - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 113478a97..53f34c9c4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v index 2b7055cd8..053caefe2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ------ Include defines: preproc flags ----- `include "fpga_defines.v" diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_defines.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_defines.v index 5088338fe..82aab8ef1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_defines.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_defines.v @@ -4,8 +4,5 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - `define ENABLE_TIMING 1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v index 81595429e..c8c3d7300 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v index 1db413a17..d7433dd3f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_clb ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v index 11bfb39db..9ff8b229f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_bottom ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v index cb1fd187c..f93e0c6ea 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_left ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v index 8535bef0b..9d0a0f05f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_right ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v index e798c6255..af8760fc5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_top ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v index 4b8581bb7..796a7b82a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: clb ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v index 6c34c9713..555071020 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: fle ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v index 02a6c9d95..aab763fac 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: ble4 ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v index 31271601f..fe3b6bc84 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v index 20f45e4f6..ae00bb2cc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v index 00c85c6ab..c1298dab4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: io ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v index 87d180da7..3fe49ce2f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v index 6457891a5..9090e22db 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v index 4e8920e9c..3e96c8986 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v index 2aa157060..67f8756a9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v index 73295a2ec..5a9c566f8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v index 8dd0bdd41..6e5f094d9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v index debeed800..221ac87b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v index 0d2862bd8..b9385b247 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v index 81bcd5c71..f8bcc9d61 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/arch_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/arch_encoder.v index 6a7ec3ee0..3a42c112a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/arch_encoder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/arch_encoder.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v index 7f6a77bac..9c69ae47b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/local_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/local_encoder.v index 63dca3f3d..49e4ef736 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/local_encoder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/local_encoder.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v index 5ab103f69..8e2d5245f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v index 2fd066540..6e40f5ac9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v index 2b188f3b5..afcf99cac 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v index 1797a11f1..9676a06d6 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v index 877cae3cb..59d6aa2b8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v index 9150689e8..1d5542b75 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- Template Verilog module for DFFSRQ ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v index cf1606882..ab3ee5445 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Verilog modules for regular wires ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index d6dcb020b..40a28f3da 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none @@ -121,6 +118,3 @@ end endmodule // ----- END Verilog module for and2_top_formal_verification_random_tb ----- -//----- Default net type ----- -`default_nettype wire - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 17d9c7e47..737c52a99 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v index 130506763..416f613c7 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ------ Include defines: preproc flags ----- `include "fpga_defines.v" diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_defines.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_defines.v index 5088338fe..82aab8ef1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_defines.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_defines.v @@ -4,8 +4,5 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - `define ENABLE_TIMING 1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v index 4d4878838..560ad7620 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v index 1db413a17..d7433dd3f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_clb ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v index 11bfb39db..9ff8b229f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_bottom ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v index cb1fd187c..f93e0c6ea 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_left ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v index 8535bef0b..9d0a0f05f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_right ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v index e798c6255..af8760fc5 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_top ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v index 4b8581bb7..796a7b82a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: clb ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v index 6c34c9713..555071020 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: fle ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v index 02a6c9d95..aab763fac 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: ble4 ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v index 31271601f..fe3b6bc84 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v index 20f45e4f6..ae00bb2cc 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v index 00c85c6ab..c1298dab4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: io ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v index 87d180da7..3fe49ce2f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v index 9c5bea24a..e96fe3e20 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v index 4f01e2579..824026109 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v index 5bdcd5aec..3982143ed 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v index 74c5af7b7..a2b0e6f8b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v index 84b692190..810565cf4 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v index 3549dbbc0..efa4cd393 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v index 429199da8..fcda836b3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v index 908c50b60..65f71ca7c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v index 3e14c89e7..d2b73b1e2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v index 269fb2521..ef9f30935 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v index 5f1119b5b..969e36e34 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v index f20a666e2..01ffd4063 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v index b0ac09abc..8a73f81e9 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v index 9e2e80db4..e12f46d4e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v index 0fe7d3a29..1d121b4fa 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/arch_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/arch_encoder.v index 6a7ec3ee0..3a42c112a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/arch_encoder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/arch_encoder.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v index 7f6a77bac..9c69ae47b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/local_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/local_encoder.v index 63dca3f3d..49e4ef736 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/local_encoder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/local_encoder.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v index 5ab103f69..8e2d5245f 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v index 54e3b3cc1..cea1b9c63 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v index 2b188f3b5..afcf99cac 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v index 7ef6296ef..8017fcc96 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v index 877cae3cb..59d6aa2b8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v index 9150689e8..1d5542b75 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- Template Verilog module for DFFSRQ ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v index cf1606882..ab3ee5445 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Verilog modules for regular wires ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index 4edf9b5bd..e9c8f977d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none @@ -121,6 +118,3 @@ end endmodule // ----- END Verilog module for and2_top_formal_verification_random_tb ----- -//----- Default net type ----- -`default_nettype wire - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v index 59666edf6..84bc42a98 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_netlists.v index e9c113a25..08d1ff068 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_netlists.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_netlists.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ------ Include defines: preproc flags ----- `include "fpga_defines.v" diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_defines.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_defines.v index 5088338fe..82aab8ef1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_defines.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_defines.v @@ -4,8 +4,5 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - `define ENABLE_TIMING 1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v index 50e97ba42..0ca441363 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v index 9e502ce3f..f14decf0c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_clb.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_clb ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v index 43c1257fa..fa26fac67 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_bottom.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_bottom ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v index 2fd852d32..7cdb12c70 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_left.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_left ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v index 6df512d13..de2aac3ad 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_right.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_right ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v index eed2bb988..fc774a284 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/grid_io_top.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Grid Verilog module: grid_io_top ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v index 810ca388b..8b9399512 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: clb ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v index 19ab0d7c6..570f33478 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: fle ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index 14f60baf9..4f990e04d 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: fabric ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v index a3cab551a..6a0ecc984 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v index a506f5e39..1c4896523 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v index 6aa162865..4a129f32b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: frac_logic ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v index a4c3e635a..76ebf7067 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v index 8aba826c3..0e33bcd20 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Physical programmable logic block Verilog module: io ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v index 9b05fb79c..a125daae0 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v index 6127be759..e28008dbe 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v index b62ba05ce..9e08b226e 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v index 76ecb10ca..7b87b1da0 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cbx_1__2_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v index f852c3062..65c1dee77 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_0__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v index fb4501a60..f948dd157 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v index 9adf53ace..545aef6b1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/cby_2__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v index 743d6f63b..041df6157 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v index 5e870301b..bed5e8b2b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v index a7eb6d355..68641a073 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_0__2_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v index 5d038999f..4b4e9fee2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v index 3140d461b..4beb5b1a8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v index 49ccccb5a..1086e2822 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_1__2_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v index 7f558fb29..d32ba8484 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__0_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v index ecb4a2050..5f916ee42 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__1_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v index 55c1736cb..3139d0aae 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/routing/sb_2__2_.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/arch_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/arch_encoder.v index 6a7ec3ee0..3a42c112a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/arch_encoder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/arch_encoder.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v index ae2d007db..9e06a1f54 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/local_encoder.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/local_encoder.v index 63dca3f3d..49e4ef736 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/local_encoder.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/local_encoder.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v index e455b5ef9..77823e3ca 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/luts.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v index 86179510a..17a8894d1 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/memories.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v index 7ff534696..5357db224 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/mux_primitives.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v index e974fdc63..f0f01ae6c 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/muxes.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v index 877cae3cb..59d6aa2b8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v @@ -4,6 +4,3 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v index 173c18752..326ed875b 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/user_defined_templates.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- Template Verilog module for DFFSRQ ----- //----- Default net type ----- `default_nettype none diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v index cf1606882..ab3ee5445 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/sub_module/wires.v @@ -4,9 +4,6 @@ // Author: Xifan TANG // Organization: University of Utah //------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - // ----- BEGIN Verilog modules for regular wires ----- //----- Default net type ----- `default_nettype none