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[Tool] Bug fix for defining global ports from tiles

This commit is contained in:
tangxifan 2020-11-10 20:31:14 -07:00
parent 05f5ce38ea
commit c61ec5a8b8
8 changed files with 58 additions and 73 deletions
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8
libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp
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@ -51,16 +51,16 @@ void read_xml_tile_global_port_annotation(pugi::xml_node& xml_tile,
TileGlobalPortId tile_global_port_id = tile_annotation.create_global_port(name_attr, tile_port_tokens[0], tile_port_parser.port());
/* Get is_clock attributes */
tile_annotation.set_global_port_is_clock(tile_global_port_id, get_attribute(xml_tile, "is_clock", loc_data).as_bool(false));
tile_annotation.set_global_port_is_clock(tile_global_port_id, get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
/* Get is_set attributes */
tile_annotation.set_global_port_is_set(tile_global_port_id, get_attribute(xml_tile, "is_set", loc_data).as_bool(false));
tile_annotation.set_global_port_is_set(tile_global_port_id, get_attribute(xml_tile, "is_set", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
/* Get is_reset attributes */
tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data).as_bool(false));
tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
/* Get default_value attributes */
tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_value", loc_data).as_int(0));
tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
}
/********************************************************************

25
openfpga/src/base/openfpga_pb_pin_fixup.cpp
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@ -17,6 +17,7 @@
#include "openfpga_side_manager.h"
#include "pb_type_utils.h"
#include "openfpga_physical_tile_utils.h"
#include "openfpga_pb_pin_fixup.h"
/* Include global variables of VPR */
@ -25,28 +26,6 @@
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Give a given pin index, find the side where this pin is located
* on the physical tile
* Note:
* - Need to check if the pin_width_offset and pin_height_offset
* are properly set in VPR!!!
*******************************************************************/
static
std::vector<e_side> find_logic_tile_pin_side(t_physical_tile_type_ptr physical_tile,
const int& physical_pin) {
std::vector<e_side> pin_sides;
for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) {
int pin_width_offset = physical_tile->pin_width_offset[physical_pin];
int pin_height_offset = physical_tile->pin_height_offset[physical_pin];
if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset][side_cand][physical_pin]) {
pin_sides.push_back(side_cand);
}
}
return pin_sides;
}
/********************************************************************
* Fix up the pb pin mapping results for a given clustered block
* 1. For each input/output pin of a clustered pb,
@ -86,7 +65,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
VTR_ASSERT(class_inf.type == RECEIVER);
rr_node_type = IPIN;
}
std::vector<e_side> pin_sides = find_logic_tile_pin_side(physical_tile, physical_pin);
std::vector<e_side> pin_sides = find_physical_tile_pin_side(physical_tile, physical_pin);
/* As some grid has height/width offset, we may not have the pin on any side */
if (0 == pin_sides.size()) {
continue;

6
openfpga/src/base/openfpga_sdc.cpp
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@ -193,17 +193,11 @@ int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
}
/* Collect global ports from the circuit library:
* TODO: should we place this in the OpenFPGA context?
*/
std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(openfpga_ctx.arch().circuit_lib);
if (true == options.generate_sdc_analysis()) {
print_analysis_sdc(options,
1./openfpga_ctx.simulation_setting().operating_clock_frequency(),
g_vpr_ctx,
openfpga_ctx,
global_ports,
openfpga_ctx.flow_manager().compress_routing());
}

26
openfpga/src/fabric/build_top_module_connection.cpp
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@ -20,6 +20,7 @@
#include "pb_type_utils.h"
#include "rr_gsb_utils.h"
#include "openfpga_physical_tile_utils.h"
#include "openfpga_device_grid_utils.h"
#include "circuit_library_utils.h"
#include "module_manager_utils.h"
@ -776,7 +777,7 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager,
for (const TileGlobalPortId& tile_global_port : tile_annotation.global_ports()) {
/* Must found one valid port! */
ModulePortId top_module_port = module_manager.find_module_port(top_module, tile_annotation.global_port_name(tile_global_port));
VTR_ASSERT(ModulePortId::INVALID() == top_module_port);
VTR_ASSERT(ModulePortId::INVALID() != top_module_port);
/* Spot the port from child modules */
for (size_t ix = 0; ix < grids.width(); ++ix) {
for (size_t iy = 0; iy < grids.height(); ++iy) {
@ -819,17 +820,20 @@ int add_top_module_global_ports_from_grid_modules(ModuleManager& module_manager,
size_t grid_pin_width = physical_tile->pin_width_offset[grid_pin_index];
size_t grid_pin_height = physical_tile->pin_height_offset[grid_pin_index];
vtr::Point<size_t> grid_coordinate(ix, iy);
std::string grid_port_name = generate_grid_port_name(grid_coordinate,
grid_pin_width, grid_pin_height,
NUM_SIDES,
grid_pin_index, false);
ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id));
std::vector<e_side> pin_sides = find_physical_tile_pin_side(physical_tile, grid_pin_index);
for (const e_side& pin_side : pin_sides) {
std::string grid_port_name = generate_grid_port_name(grid_coordinate,
grid_pin_width, grid_pin_height,
pin_side,
grid_pin_index, false);
ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_port_id));
/* Build nets */
add_module_bus_nets(module_manager, top_module,
top_module, 0, top_module_port,
grid_module, grid_instance, grid_port_id);
/* Build nets */
add_module_bus_nets(module_manager, top_module,
top_module, 0, top_module_port,
grid_module, grid_instance, grid_port_id);
}
}
}
}

41
openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
View File

@ -44,8 +44,7 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
const IoLocationMap& io_location_map,
const ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports,
const FabricGlobalPortInfo& fabric_global_port_info,
const float& critical_path_delay) {
/* Validate the file stream */
valid_file_stream(fp);
@ -57,17 +56,17 @@ void print_analysis_sdc_io_delays(std::fstream& fp,
/* Get clock port from the global port */
std::vector<BasicPort> operating_clock_ports;
for (const CircuitPortId& clock_port : global_ports) {
if (CIRCUIT_MODEL_PORT_CLOCK != circuit_lib.port_type(clock_port)) {
for (const FabricGlobalPortId& clock_port : fabric_global_port_info.global_ports()) {
if (false == fabric_global_port_info.global_port_is_clock(clock_port)) {
continue;
}
/* We only constrain operating clock here! */
if (true == circuit_lib.port_is_prog(clock_port)) {
if (true == fabric_global_port_info.global_port_is_prog(clock_port)) {
continue;
}
/* Find the module port and Update the operating port list */
ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(clock_port));
ModulePortId module_port = fabric_global_port_info.global_module_port(clock_port);
operating_clock_ports.push_back(module_manager.module_port(top_module, module_port));
}
@ -181,8 +180,7 @@ static
void print_analysis_sdc_disable_global_ports(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const std::vector<CircuitPortId>& global_ports) {
const FabricGlobalPortInfo& fabric_global_port_info) {
/* Validate file stream */
valid_file_stream(fp);
@ -191,31 +189,19 @@ void print_analysis_sdc_disable_global_ports(std::fstream& fp,
fp << "# Disable timing for global ports " << std::endl;
fp << "##################################################" << std::endl;
for (const CircuitPortId& global_port : global_ports) {
for (const FabricGlobalPortId& global_port : fabric_global_port_info.global_ports()) {
/* Skip operating clock here! */
if ( (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(global_port))
&& (false == circuit_lib.port_is_prog(global_port)) ) {
if ( (true == fabric_global_port_info.global_port_is_clock(global_port))
&& (false == fabric_global_port_info.global_port_is_prog(global_port)) ) {
continue;
}
/* Skip any gpio port here! */
if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(global_port))
&& (true == circuit_lib.port_is_io(global_port)) ) {
if (true == fabric_global_port_info.global_port_is_io(global_port)) {
continue;
}
/* Skip any gpio port here! */
if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(global_port)) {
continue;
}
/* Skip any gpio port here! */
if ( (CIRCUIT_MODEL_PORT_INOUT == circuit_lib.port_type(global_port))
&& (true == circuit_lib.port_is_io(global_port)) ) {
continue;
}
ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port));
ModulePortId module_port = fabric_global_port_info.global_module_port(global_port);
BasicPort port_to_disable = module_manager.module_port(top_module, module_port);
print_sdc_disable_port_timing(fp, port_to_disable);
@ -230,7 +216,6 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
const float& critical_path_delay,
const VprContext& vpr_ctx,
const OpenfpgaContext& openfpga_ctx,
const std::vector<CircuitPortId>& global_ports,
const bool& compact_routing_hierarchy) {
/* Create the file name for Verilog netlist */
std::string sdc_fname(option.sdc_dir() + generate_analysis_sdc_file_name(vpr_ctx.atom().nlist.netlist_name(), std::string(SDC_ANALYSIS_FILE_NAME)));
@ -261,13 +246,13 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
vpr_ctx.atom(), vpr_ctx.placement(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.io_location_map(),
openfpga_ctx.module_graph(), top_module,
openfpga_ctx.arch().circuit_lib, global_ports,
openfpga_ctx.fabric_global_port_info(),
critical_path_delay);
/* Disable the timing for global ports */
print_analysis_sdc_disable_global_ports(fp,
openfpga_ctx.module_graph(), top_module,
openfpga_ctx.arch().circuit_lib, global_ports);
openfpga_ctx.fabric_global_port_info());
/* Disable the timing for configuration cells */
rec_print_pnr_sdc_disable_configurable_memory_module_output(fp, option.flatten_names(),

1
openfpga/src/fpga_sdc/analysis_sdc_writer.h
View File

@ -21,7 +21,6 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
const float& critical_path_delay,
const VprContext& vpr_ctx,
const OpenfpgaContext& openfpga_ctx,
const std::vector<CircuitPortId>& global_ports,
const bool& compact_routing_hierarchy);
} /* end namespace openfpga */

21
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -14,6 +14,27 @@
/* begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Give a given pin index, find the side where this pin is located
* on the physical tile
* Note:
* - Need to check if the pin_width_offset and pin_height_offset
* are properly set in VPR!!!
*******************************************************************/
std::vector<e_side> find_physical_tile_pin_side(t_physical_tile_type_ptr physical_tile,
const int& physical_pin) {
std::vector<e_side> pin_sides;
for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) {
int pin_width_offset = physical_tile->pin_width_offset[physical_pin];
int pin_height_offset = physical_tile->pin_height_offset[physical_pin];
if (true == physical_tile->pinloc[pin_width_offset][pin_height_offset][side_cand][physical_pin]) {
pin_sides.push_back(side_cand);
}
}
return pin_sides;
}
/********************************************************************
* Find the Fc of a pin in physical tile
*******************************************************************/

3
openfpga/src/utils/openfpga_physical_tile_utils.h
View File

@ -17,6 +17,9 @@
/* begin namespace openfpga */
namespace openfpga {
std::vector<e_side> find_physical_tile_pin_side(t_physical_tile_type_ptr physical_tile,
const int& physical_pin);
float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type,
const int& pin);