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[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file

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tangxifan 2021-03-08 21:09:23 -07:00
parent 131643dcc0
commit c53c41b7a5
1 changed files with 1 additions and 1 deletions
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openfpga_flow/misc/qlf_yosys.ys
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@ -4,4 +4,4 @@ ${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS} synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
write_verilog -noattr -nohex ${TOP_MODULE}.v write_verilog -noattr -nohex ${OUTPUT_VERILOG}.v