From c53c41b7a5c48b54d028d3f859779208a7fd1ddc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Mar 2021 21:09:23 -0700 Subject: [PATCH] [Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file --- openfpga_flow/misc/qlf_yosys.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys index c90b8c5ac..e0b530564 100644 --- a/openfpga_flow/misc/qlf_yosys.ys +++ b/openfpga_flow/misc/qlf_yosys.ys @@ -4,4 +4,4 @@ ${READ_VERILOG_FILE} synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS} -write_verilog -noattr -nohex ${TOP_MODULE}.v \ No newline at end of file +write_verilog -noattr -nohex ${OUTPUT_VERILOG}.v