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keep debugging tile direct connections

This commit is contained in:
tangxifan 2020-03-20 15:10:00 -06:00
parent a46fc9f028
commit c5049a1ec8
2 changed files with 9 additions and 2 deletions
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2
openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
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@ -210,7 +210,7 @@
<segment name="L4" circuit_model_name="chan_segment"/> <segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment> </routing_segment>
<direct_connection> <direct_connection>
<direct name="adder" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->

9
openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
View File

@ -147,7 +147,14 @@
<fc_override port_name="cin" fc_type="frac" fc_val="0"/> <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
<fc_override port_name="cout" fc_type="frac" fc_val="0"/> <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
</fc> </fc>
<pinlocations pattern="spread"/> <!-- Highly recommand to customize pin location when direct connection is used!!! -->
<!--pinlocations pattern="spread"/-->
<pinlocations pattern="custom">
<loc side="left">clb.clk</loc>
<loc side="top">clb.cin</loc>
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
</pinlocations>
</tile> </tile>
</tiles> </tiles>
<!-- ODIN II specific config ends --> <!-- ODIN II specific config ends -->