From c5049a1ec83c25ee2282fa2ee38575b0a4ebf457 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 20 Mar 2020 15:10:00 -0600
Subject: [PATCH] keep debugging tile direct connections

---
 .../k6_frac_N10_adder_chain_40nm_openfpga.xml            | 2 +-
 openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml  | 9 ++++++++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index 2b340168e..98823698f 100644
--- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -210,7 +210,7 @@
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
   <direct_connection>
-    <direct name="adder" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index ed928c98d..ed6e2defc 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -147,7 +147,14 @@
         <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
         <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
       </fc>
-      <pinlocations pattern="spread"/>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
     </tile>
   </tiles>
   <!-- ODIN II specific config ends -->