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[core] code format

This commit is contained in:
tangxifan 2023-09-25 22:34:39 -07:00
parent 262e47a922
commit c4bce834e4
3 changed files with 26 additions and 28 deletions
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12
openfpga/src/fabric/build_device_module.cpp
View File

@ -121,14 +121,12 @@ int build_device_module_graph(
return status;
}
/* Build the modules */
build_tile_modules(module_manager, decoder_lib, openfpga_ctx.fabric_tile(),
vpr_device_ctx.grid,
openfpga_ctx.vpr_device_annotation(),
build_tile_modules(
module_manager, decoder_lib, openfpga_ctx.fabric_tile(),
vpr_device_ctx.grid, openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
openfpga_ctx.arch().tile_annotations,
openfpga_ctx.arch().circuit_lib,
sram_model,
openfpga_ctx.arch().config_protocol.type(),
openfpga_ctx.arch().tile_annotations, openfpga_ctx.arch().circuit_lib,
sram_model, openfpga_ctx.arch().config_protocol.type(),
name_module_using_index, frame_view, verbose);
}

34
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1004,10 +1004,10 @@ static int build_tile_port_and_nets_from_pb(
ModuleManager& module_manager, const ModuleId& tile_module,
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph,
const TileAnnotation& tile_annotation,
const vtr::Point<size_t>& pb_coord, const std::vector<size_t>& pb_instances,
const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
const size_t& ipb, const bool& frame_view, const bool& verbose) {
const TileAnnotation& tile_annotation, const vtr::Point<size_t>& pb_coord,
const std::vector<size_t>& pb_instances, const FabricTile& fabric_tile,
const FabricTileId& curr_fabric_tile_id, const size_t& ipb,
const bool& frame_view, const bool& verbose) {
size_t pb_instance = pb_instances[ipb];
t_physical_tile_type_ptr phy_tile = grids.get_physical_type(
t_physical_tile_loc(pb_coord.x(), pb_coord.y(), layer));
@ -1066,8 +1066,7 @@ static int build_tile_port_and_nets_from_pb(
subtile_index < phy_tile->capacity);
std::string port_name = generate_grid_port_name(
iwidth, iheight, subtile_index, side, pin_info);
if (tile_annotation.is_tile_port_to_merge(
std::string(phy_tile->name),
if (tile_annotation.is_tile_port_to_merge(std::string(phy_tile->name),
pin_info.get_name())) {
if (subtile_index == 0) {
port_name = generate_grid_port_name(0, 0, 0, TOP, pin_info);
@ -1203,9 +1202,8 @@ static int build_tile_module_ports_and_nets(
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id,
const std::vector<size_t>& pb_instances,
const TileAnnotation& tile_annotation, const FabricTile& fabric_tile,
const FabricTileId& fabric_tile_id, const std::vector<size_t>& pb_instances,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
const std::vector<size_t>& sb_instances, const bool& name_module_using_index,
const bool& frame_view, const bool& verbose) {
@ -1270,8 +1268,8 @@ static int build_tile_module_ports_and_nets(
fabric_tile.pb_coordinates(fabric_tile_id)[ipb];
status_code = build_tile_port_and_nets_from_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation,
rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb,
frame_view, verbose);
rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile,
fabric_tile_id, ipb, frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1314,8 +1312,8 @@ static int build_tile_module(
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const TileAnnotation& tile_annotation, const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index, const bool& frame_view,
const bool& verbose) {
@ -1463,8 +1461,9 @@ static int build_tile_module(
/* Add module nets and ports */
status_code = build_tile_module_ports_and_nets(
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id, pb_instances,
cb_instances, sb_instances, name_module_using_index, frame_view, verbose);
device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id,
pb_instances, cb_instances, sb_instances, name_module_using_index,
frame_view, verbose);
/* Add global ports to the pb_module:
* This is a much easier job after adding sub modules (instances),
@ -1549,8 +1548,9 @@ int build_tile_modules(ModuleManager& module_manager,
for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) {
status_code = build_tile_module(
module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer,
vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, circuit_lib,
sram_model, sram_orgz_type, name_module_using_index, frame_view, verbose);
vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation,
circuit_lib, sram_model, sram_orgz_type, name_module_using_index,
frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}

2
openfpga/src/fabric/build_tile_modules.h
View File

@ -15,8 +15,8 @@
#include "fabric_tile.h"
#include "module_manager.h"
#include "rr_graph_view.h"
#include "vpr_device_annotation.h"
#include "tile_annotation.h"
#include "vpr_device_annotation.h"
/********************************************************************
* Function declaration