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[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit

This commit is contained in:
tangxifan 2022-09-01 20:10:29 -07:00
parent d3f08a893c
commit c48f750f86
3 changed files with 9 additions and 2 deletions
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2
openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
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@ -18,7 +18,7 @@ run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_
echo -e "Testing bitstream generation for an 96x96 FPGA device"; echo -e "Testing bitstream generation for an 96x96 FPGA device";
run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@ run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@
run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_96x96 $@ run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_72x72 $@
echo -e "Testing loading architecture bitstream from an external file"; echo -e "Testing loading architecture bitstream from an external file";
run-task fpga_bitstream/load_external_architecture_bitstream $@ run-task fpga_bitstream/load_external_architecture_bitstream $@

2
openfpga_flow/tasks/fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_96x96/config/task.conf → openfpga_flow/tasks/fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_72x72/config/task.conf
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@ -21,7 +21,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_route_chan_width=100 openfpga_vpr_route_chan_width=100
openfpga_vpr_device_layout=96x96 openfpga_vpr_device_layout=72x72
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml

7
openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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@ -91,6 +91,13 @@
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
<fixed_layout name="72x72" width="74" height="74">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>
<corners type="EMPTY" priority="101"/>
<!--Fill with 'clb'-->
<fill type="clb" priority="10"/>
</fixed_layout>
<fixed_layout name="96x96" width="98" height="98"> <fixed_layout name="96x96" width="98" height="98">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners--> <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/> <perimeter type="io" priority="100"/>