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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI

This commit is contained in:
tangxifan 2020-09-14 16:16:03 -06:00
parent f149c88548
commit c31d36deb6
2 changed files with 4 additions and 1 deletions
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3
.travis/fpga_verilog_reg_test.sh
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@ -61,6 +61,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux
echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
echo -e "Testing Verilog generation with behavioral description";
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs

2
libopenfpga/libarchopenfpga/src/circuit_library.cpp
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@ -1963,7 +1963,7 @@ void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) {
/* Get the circuit model id by name, skip those with empty names*/
for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) {
if (true == buffer_model_names_[model_id][buffer_id].empty()) {
return;
continue;
}
buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]);
}