From c31d36deb63b8fb0c1275249a56a47b3c0906af4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Sep 2020 16:16:03 -0600 Subject: [PATCH] [Regression Tests] Deploy output buffer only routing multiplexer testcase to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ libopenfpga/libarchopenfpga/src/circuit_library.cpp | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index 0a46dd5de..35086b65b 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -61,6 +61,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux echo -e "Testing Verilog generation with routing multiplexers with input buffers only"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs +echo -e "Testing Verilog generation with routing multiplexers with output buffers only"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs + echo -e "Testing Verilog generation with behavioral description"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index 881035ee7..42df84407 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -1963,7 +1963,7 @@ void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) { /* Get the circuit model id by name, skip those with empty names*/ for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) { if (true == buffer_model_names_[model_id][buffer_id].empty()) { - return; + continue; } buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]); }