[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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@ -61,6 +61,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux
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echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
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echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
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echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
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echo -e "Testing Verilog generation with behavioral description";
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echo -e "Testing Verilog generation with behavioral description";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
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@ -1963,7 +1963,7 @@ void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) {
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/* Get the circuit model id by name, skip those with empty names*/
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/* Get the circuit model id by name, skip those with empty names*/
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for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) {
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for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) {
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if (true == buffer_model_names_[model_id][buffer_id].empty()) {
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if (true == buffer_model_names_[model_id][buffer_id].empty()) {
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return;
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continue;
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}
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}
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buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]);
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buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]);
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}
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}
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