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bug fix for RC delay computing in SDC generation

This commit is contained in:
tangxifan 2020-04-20 22:20:00 -06:00
parent 1a8968cb37
commit c2804a4c1f
1 changed files with 8 additions and 1 deletions
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9
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
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@ -356,7 +356,14 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir,
/* Connection block routing segment ids for each track */
RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack);
float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal;
/* Computing the delay of the routing segment
* Here we just assume a simple 1-level RC delay model
* TODO: Should consider multi-level RC delay models
* where the number of levels are defined by users
*/
float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal
* rr_graph.get_segment(segment_id).Cmetal;
/* If we have a zero-delay path to contrain, we will skip unless users want so */
if ( (false == constrain_zero_delay_paths)