From c2804a4c1f04810f315f0a630781a09b44dcc9fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 20 Apr 2020 22:20:00 -0600 Subject: [PATCH] bug fix for RC delay computing in SDC generation --- openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp index a73ad8d30..4bed8f16a 100644 --- a/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp +++ b/openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp @@ -356,7 +356,14 @@ void print_pnr_sdc_constrain_cb_timing(const std::string& sdc_dir, /* Connection block routing segment ids for each track */ RRSegmentId segment_id = rr_gsb.get_chan_node_segment(rr_gsb.get_cb_chan_side(cb_type), itrack); - float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal; + + /* Computing the delay of the routing segment + * Here we just assume a simple 1-level RC delay model + * TODO: Should consider multi-level RC delay models + * where the number of levels are defined by users + */ + float routing_segment_delay = rr_graph.get_segment(segment_id).Rmetal + * rr_graph.get_segment(segment_id).Cmetal; /* If we have a zero-delay path to contrain, we will skip unless users want so */ if ( (false == constrain_zero_delay_paths)