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[script] change default tool paths for OpenFPGA flow scripts

This commit is contained in:
tangxifan 2022-08-18 11:02:21 -07:00
parent 7319ded98f
commit c0b1d76a5e
1 changed files with 5 additions and 5 deletions
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10
openfpga_flow/misc/fpgaflow_default_tool_path.conf
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@ -1,14 +1,14 @@
# Standard Configuration Example
[CAD_TOOLS_PATH]
openfpga_shell_path = ${PATH:OPENFPGA_PATH}/openfpga/openfpga
openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
vpr_path = ${PATH:OPENFPGA_PATH}/vpr/vpr
ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace
abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
ace_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/ace2/ace
pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
iverilog_path = iverilog
include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists