diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
index b0b25b100..7c3e49803 100644
--- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf
+++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
@@ -1,14 +1,14 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
-openfpga_shell_path = ${PATH:OPENFPGA_PATH}/openfpga/openfpga
+openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
 yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
 abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
-abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
-abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
-vpr_path = ${PATH:OPENFPGA_PATH}/vpr/vpr
-ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace
+abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
+abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
+vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
+ace_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/ace2/ace
 pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
 iverilog_path = iverilog
 include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists