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[FPGA-Verilog] Correct bugs in logging clock frequencies

This commit is contained in:
tangxifan 2021-10-06 11:55:57 -07:00
parent fcb5470baa
commit bf473f50f8
3 changed files with 14 additions and 14 deletions
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4
libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
View File

@ -84,7 +84,7 @@ std::string unit_to_string(const float& unit) {
* Convert numeric time unit to string
* e.g. 1e-12 -> ps
*******************************************************************/
std::string time_unit_to_string(const float& unit) {
std::string time_unit_to_string(const float& unit, const std::string& postfix) {
/* For larger than 1 unit, we do not accept */
if (1e6 < unit) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
@ -93,7 +93,7 @@ std::string time_unit_to_string(const float& unit) {
exit(1);
}
return unit_to_string(unit) + std::string("s");
return unit_to_string(unit) + postfix;
}
/********************************************************************

2
libopenfpga/libopenfpgautil/src/openfpga_scale.h
View File

@ -18,7 +18,7 @@ bool same_float_number(const float& a,
std::string unit_to_string(const float& unit);
std::string time_unit_to_string(const float& unit);
std::string time_unit_to_string(const float& unit, const std::string& postfix = "s");
float string_to_unit(const std::string& scale);

22
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
View File

@ -299,15 +299,15 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si
/* Bypass all the clocks which does not match */
if (sim_settings.clock_port(sim_clk) == sr_clock_port && sim_settings.constrained_clock(sim_clk)) {
if (sr_clock_period > 0.5 * (1 / sim_settings.clock_frequency(sim_clk)) / timescale) {
VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s[Hz])! Shift register chain cannot load data completely!\n",
1. / (2. * sr_clock_period) / 1e6,
time_unit_to_string(1e6).c_str());
VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s)! Shift register chain cannot load data completely!\n",
1. / (2. * sr_clock_period * timescale) / 1e6,
time_unit_to_string(1e6, "Hz").c_str());
return CMD_EXEC_FATAL_ERROR;
} else {
sr_clock_period = 0.5 * (1. / sim_settings.clock_frequency(sim_clk)) / timescale;
VTR_LOG("Will use constrained clock frequency (=%g %s[Hz]) for %s.\n",
VTR_LOG("Will use constrained clock frequency (=%g %s) for %s.\n",
sim_settings.clock_frequency(sim_clk) / 1e6,
time_unit_to_string(1e6).c_str(),
time_unit_to_string(1e6, "Hz").c_str(),
sr_clock_port.get_name().c_str());
}
}
@ -357,14 +357,14 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(s
float bl_sr_clock_period = 0.25 * prog_clock_period / (fabric_bits_by_addr.bl_word_size() + 2) / timescale;
float wl_sr_clock_period = 0.25 * prog_clock_period / (fabric_bits_by_addr.wl_word_size() + 2) / timescale;
VTR_LOG("Precomputed clock frequency (=%g %s[Hz]) for %s.\n",
1. / (2. * bl_sr_clock_period) / 1e6,
time_unit_to_string(1e6).c_str(),
VTR_LOG("Precomputed clock frequency (=%g %s) for %s.\n",
1. / (2. * bl_sr_clock_period * timescale) / 1e6,
time_unit_to_string(1e6, "Hz").c_str(),
bl_sr_clock_port.get_name().c_str());
VTR_LOG("Precomputed clock frequency (=%g %s[Hz]) for %s.\n",
1. / (2. * wl_sr_clock_period) / 1e6,
time_unit_to_string(1e6).c_str(),
VTR_LOG("Precomputed clock frequency (=%g %s) for %s.\n",
1. / (2. * wl_sr_clock_period * timescale) / 1e6,
time_unit_to_string(1e6, "Hz").c_str(),
wl_sr_clock_port.get_name().c_str());
if (CMD_EXEC_FATAL_ERROR == constrain_blwl_shift_register_clock_period_from_simulation_settings(sim_settings,