From bf473f50f8f618e97b84407c52dfd73d9a906e8a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Oct 2021 11:55:57 -0700 Subject: [PATCH] [FPGA-Verilog] Correct bugs in logging clock frequencies --- .../libopenfpgautil/src/openfpga_scale.cpp | 4 ++-- .../libopenfpgautil/src/openfpga_scale.h | 2 +- .../verilog_top_testbench_memory_bank.cpp | 22 +++++++++---------- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp b/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp index 66364501d..222d1c41b 100644 --- a/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp +++ b/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp @@ -84,7 +84,7 @@ std::string unit_to_string(const float& unit) { * Convert numeric time unit to string * e.g. 1e-12 -> ps *******************************************************************/ -std::string time_unit_to_string(const float& unit) { +std::string time_unit_to_string(const float& unit, const std::string& postfix) { /* For larger than 1 unit, we do not accept */ if (1e6 < unit) { VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -93,7 +93,7 @@ std::string time_unit_to_string(const float& unit) { exit(1); } - return unit_to_string(unit) + std::string("s"); + return unit_to_string(unit) + postfix; } /******************************************************************** diff --git a/libopenfpga/libopenfpgautil/src/openfpga_scale.h b/libopenfpga/libopenfpgautil/src/openfpga_scale.h index 197923548..f10abcca6 100644 --- a/libopenfpga/libopenfpgautil/src/openfpga_scale.h +++ b/libopenfpga/libopenfpgautil/src/openfpga_scale.h @@ -18,7 +18,7 @@ bool same_float_number(const float& a, std::string unit_to_string(const float& unit); -std::string time_unit_to_string(const float& unit); +std::string time_unit_to_string(const float& unit, const std::string& postfix = "s"); float string_to_unit(const std::string& scale); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp index 718e1688a..12fc89139 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp @@ -299,15 +299,15 @@ int constrain_blwl_shift_register_clock_period_from_simulation_settings(const Si /* Bypass all the clocks which does not match */ if (sim_settings.clock_port(sim_clk) == sr_clock_port && sim_settings.constrained_clock(sim_clk)) { if (sr_clock_period > 0.5 * (1 / sim_settings.clock_frequency(sim_clk)) / timescale) { - VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s[Hz])! Shift register chain cannot load data completely!\n", - 1. / (2. * sr_clock_period) / 1e6, - time_unit_to_string(1e6).c_str()); + VTR_LOG_ERROR("Constrained clock frequency for BL shift registers is lower than the minimum requirement (%g %s)! Shift register chain cannot load data completely!\n", + 1. / (2. * sr_clock_period * timescale) / 1e6, + time_unit_to_string(1e6, "Hz").c_str()); return CMD_EXEC_FATAL_ERROR; } else { sr_clock_period = 0.5 * (1. / sim_settings.clock_frequency(sim_clk)) / timescale; - VTR_LOG("Will use constrained clock frequency (=%g %s[Hz]) for %s.\n", + VTR_LOG("Will use constrained clock frequency (=%g %s) for %s.\n", sim_settings.clock_frequency(sim_clk) / 1e6, - time_unit_to_string(1e6).c_str(), + time_unit_to_string(1e6, "Hz").c_str(), sr_clock_port.get_name().c_str()); } } @@ -357,14 +357,14 @@ int print_verilog_top_testbench_configuration_protocol_ql_memory_bank_stimulus(s float bl_sr_clock_period = 0.25 * prog_clock_period / (fabric_bits_by_addr.bl_word_size() + 2) / timescale; float wl_sr_clock_period = 0.25 * prog_clock_period / (fabric_bits_by_addr.wl_word_size() + 2) / timescale; - VTR_LOG("Precomputed clock frequency (=%g %s[Hz]) for %s.\n", - 1. / (2. * bl_sr_clock_period) / 1e6, - time_unit_to_string(1e6).c_str(), + VTR_LOG("Precomputed clock frequency (=%g %s) for %s.\n", + 1. / (2. * bl_sr_clock_period * timescale) / 1e6, + time_unit_to_string(1e6, "Hz").c_str(), bl_sr_clock_port.get_name().c_str()); - VTR_LOG("Precomputed clock frequency (=%g %s[Hz]) for %s.\n", - 1. / (2. * wl_sr_clock_period) / 1e6, - time_unit_to_string(1e6).c_str(), + VTR_LOG("Precomputed clock frequency (=%g %s) for %s.\n", + 1. / (2. * wl_sr_clock_period * timescale) / 1e6, + time_unit_to_string(1e6, "Hz").c_str(), wl_sr_clock_port.get_name().c_str()); if (CMD_EXEC_FATAL_ERROR == constrain_blwl_shift_register_clock_period_from_simulation_settings(sim_settings,