replace hyperlink with more stable :ref: link
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@ -5,7 +5,7 @@ Introduction and Setup
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**In this tutorial, we will**
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**In this tutorial, we will**
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- Provide the motivation for generating the user_defined_template.v verilog file
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- Provide the motivation for generating the user_defined_template.v verilog file
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- Go through a generated user_defined_template.v file to demonstrate how to use it
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- Go through a generated user_defined_template.v file to demonstrate how to use it
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Through this tutorial, we will show how and when to use the ``user_defined_template.v`` file.
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Through this tutorial, we will show how and when to use the :ref:`cmdoption-arg-user_defined_templates.v` file.
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To begin the tutorial, we start with a modified version of the hard adder task that comes with OpenFPGA.
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To begin the tutorial, we start with a modified version of the hard adder task that comes with OpenFPGA.
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To follow along, go to the root directory of OpenFPGA and enter:
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To follow along, go to the root directory of OpenFPGA and enter:
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@ -85,7 +85,7 @@ The task should now complete without any errors.
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Fixing the Error with user_defined_template.v
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Fixing the Error with user_defined_template.v
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The `user_defined_template.v`_ file can be found starting from the root directory and entering:
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The :ref:`cmdoption-arg-user_defined_templates.v` file can be found starting from the root directory and entering:
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.. code-block:: bash
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.. code-block:: bash
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@ -167,4 +167,3 @@ Finally, rerun this command from the OpenFPGA root directory to ensure it is wor
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python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
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python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
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.. _user_defined_template.v: https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/fabric_netlist/#cmdoption-arg-user_defined_templates.v
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