From beed1ce31e40540d42775a709bcab371a1bbeb44 Mon Sep 17 00:00:00 2001 From: bbleaptrot <35536624+bbleaptrot@users.noreply.github.com> Date: Mon, 19 Apr 2021 08:38:09 -0600 Subject: [PATCH] replace hyperlink with more stable :ref: link --- .../tutorials/arch_modeling/user_defined_temp_tutorial.rst | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst index cbc161971..6e55bbddf 100644 --- a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst +++ b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst @@ -5,7 +5,7 @@ Introduction and Setup **In this tutorial, we will** - Provide the motivation for generating the user_defined_template.v verilog file - Go through a generated user_defined_template.v file to demonstrate how to use it -Through this tutorial, we will show how and when to use the ``user_defined_template.v`` file. +Through this tutorial, we will show how and when to use the :ref:`cmdoption-arg-user_defined_templates.v` file. To begin the tutorial, we start with a modified version of the hard adder task that comes with OpenFPGA. To follow along, go to the root directory of OpenFPGA and enter: @@ -85,7 +85,7 @@ The task should now complete without any errors. Fixing the Error with user_defined_template.v ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The `user_defined_template.v`_ file can be found starting from the root directory and entering: +The :ref:`cmdoption-arg-user_defined_templates.v` file can be found starting from the root directory and entering: .. code-block:: bash @@ -167,4 +167,3 @@ Finally, rerun this command from the OpenFPGA root directory to ensure it is wor python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs -.. _user_defined_template.v: https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/fabric_netlist/#cmdoption-arg-user_defined_templates.v