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[Doc] Update documentation about don't care bit in frame address

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tangxifan 2020-10-30 22:13:28 -06:00
parent 6b25cf720d
commit be7f7592ae
1 changed files with 5 additions and 1 deletions
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6
docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
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@ -47,6 +47,8 @@ The information depends on the type of configuration procotol.
.. option:: frame_based .. option:: frame_based
Multiple lines will be included, each of which is organized as <address><space><bit>. Multiple lines will be included, each of which is organized as <address><space><bit>.
Note that the address may include don't care bit which is denoted as ``x``.
OpenFPGA automatically convert don't care bit to logic ``0`` when generating testbenches.
For example For example
.. code-block:: xml .. code-block:: xml
@ -97,10 +99,12 @@ Other information may depend on the type of configuration procotol.
- ``frame``: frame address information - ``frame``: frame address information
.. note:: Frame address may include don't care bit which is denoted as ``x``.
A quick example: A quick example:
.. code-block:: xml .. code-block:: xml
<bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/> <bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
<frame address="0000000000000000"/> <frame address="0001000x00000x01"/>
</bit> </bit>