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[core] fixed syntax errors

This commit is contained in:
tangxifan 2023-04-23 14:26:08 +08:00
parent 592765af48
commit bd511ba515
8 changed files with 40 additions and 24 deletions
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35
libs/libarchopenfpga/src/config_protocol.cpp
View File

@ -26,11 +26,18 @@ CircuitModelId ConfigProtocol::memory_model() const { return memory_model_; }
int ConfigProtocol::num_regions() const { return num_regions_; } int ConfigProtocol::num_regions() const { return num_regions_; }
std::vector<openfpga::BasicPort> ConfigProtocol::prog_clock_port_info() const { size_t ConfigProtocol::num_prog_clocks() const {
VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
return prog_clk_port_.get_width();
}
openfpga::BasicPort ConfigProtocol::prog_clock_port_info() const {
VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
return prog_clk_port_; return prog_clk_port_;
} }
std::vector<openfpga::BasicPort> ConfigProtocol::prog_clock_pins() const { std::vector<openfpga::BasicPort> ConfigProtocol::prog_clock_pins() const {
VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
std::vector<openfpga::BasicPort> keys; std::vector<openfpga::BasicPort> keys;
for (auto pin : prog_clk_port_.pins()) { for (auto pin : prog_clk_port_.pins()) {
keys.push_back(openfpga::BasicPort(prog_clk_port_.get_name(), pin, pin)); keys.push_back(openfpga::BasicPort(prog_clk_port_.get_name(), pin, pin));
@ -38,10 +45,11 @@ std::vector<openfpga::BasicPort> ConfigProtocol::prog_clock_pins() const {
return keys; return keys;
} }
std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str( std::string ConfigProtocol::prog_clock_pin_ccff_head_indices_str(
const openfpga::BasicPort& port) const { const openfpga::BasicPort& port) const {
VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
std::string ret(""); std::string ret("");
std::vector<size_t> raw = prog_clock_port_ccff_head_indices(port); std::vector<size_t> raw = prog_clock_pin_ccff_head_indices(port);
if (!raw.empty()) { if (!raw.empty()) {
for (size_t idx : raw) { for (size_t idx : raw) {
/* TODO: We need a join function */ /* TODO: We need a join function */
@ -53,13 +61,14 @@ std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str(
return ret; return ret;
} }
std::vector<size_t> ConfigProtocol::prog_clock_port_ccff_head_indices( std::vector<size_t> ConfigProtocol::prog_clock_pin_ccff_head_indices(
const openfpga::BasicPort& port) const { const openfpga::BasicPort& port) const {
VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN);
std::vector<size_t> ret; std::vector<size_t> ret;
if (port.get_width() != 1) { if (port.get_width() != 1) {
VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width()); VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width());
} }
VTR_ASSERT(port.get_width == 1); VTR_ASSERT(port.get_width() == 1);
if (!prog_clk_port_.contained(port)) { if (!prog_clk_port_.contained(port)) {
VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb()); VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb());
} }
@ -115,12 +124,12 @@ void ConfigProtocol::set_num_regions(const int& num_regions) {
num_regions_ = num_regions; num_regions_ = num_regions;
} }
void ConfigProtocol::set_prog_clock(const openfpga::BasicPort& port) { void ConfigProtocol::set_prog_clock_port(const openfpga::BasicPort& port) {
prog_clk_port_ = port; prog_clk_port_ = port;
prog_clk_ccff_head_indices_.resize(prog_clk_port_.get_width()); prog_clk_ccff_head_indices_.resize(prog_clk_port_.get_width());
} }
void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair( void ConfigProtocol::set_prog_clock_pin_ccff_head_indices_pair(
const openfpga::BasicPort& port, const std::string& indices_str) { const openfpga::BasicPort& port, const std::string& indices_str) {
openfpga::StringToken tokenizer(indices_str); openfpga::StringToken tokenizer(indices_str);
std::vector<size_t> token_int; std::vector<size_t> token_int;
@ -131,7 +140,7 @@ void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(
if (port.get_width() != 1) { if (port.get_width() != 1) {
VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width()); VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width());
} }
VTR_ASSERT(port.get_width == 1); VTR_ASSERT(port.get_width() == 1);
if (!prog_clk_port_.contained(port)) { if (!prog_clk_port_.contained(port)) {
VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb()); VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb());
} }
@ -141,7 +150,7 @@ void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair(
"Overwrite the pair between programming clock port '%s[%d:%d]' and ccff " "Overwrite the pair between programming clock port '%s[%d:%d]' and ccff "
"head indices (previous: '%s', current: '%s')!\n", "head indices (previous: '%s', current: '%s')!\n",
port.get_name().c_str(), port.get_lsb(), port.get_msb(), port.get_name().c_str(), port.get_lsb(), port.get_msb(),
prog_clock_port_ccff_head_indices_str(port).c_str(), indices_str.c_str()); prog_clock_pin_ccff_head_indices_str(port).c_str(), indices_str.c_str());
} }
prog_clk_ccff_head_indices_[port.get_lsb()] = token_int; prog_clk_ccff_head_indices_[port.get_lsb()] = token_int;
} }
@ -235,7 +244,7 @@ int ConfigProtocol::validate_ccff_prog_clocks() const {
int num_err = 0; int num_err = 0;
/* Initialize scoreboard */ /* Initialize scoreboard */
std::vector<int> ccff_head_scoreboard(num_regions(), 0); std::vector<int> ccff_head_scoreboard(num_regions(), 0);
for (openfpga::BasicPort port : prog_clock_ports()) { for (openfpga::BasicPort port : prog_clock_pins()) {
/* Must be valid first */ /* Must be valid first */
if (port.is_valid()) { if (port.is_valid()) {
VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n", VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n",
@ -251,7 +260,7 @@ int ConfigProtocol::validate_ccff_prog_clocks() const {
num_err++; num_err++;
} }
/* Fill scoreboard */ /* Fill scoreboard */
for (size_t ccff_head_idx : prog_clock_port_ccff_head_indices(port)) { for (size_t ccff_head_idx : prog_clock_pin_ccff_head_indices(port)) {
if (ccff_head_idx >= ccff_head_scoreboard.size()) { if (ccff_head_idx >= ccff_head_scoreboard.size()) {
VTR_LOG_ERROR( VTR_LOG_ERROR(
"Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' " "Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' "
@ -263,11 +272,11 @@ int ConfigProtocol::validate_ccff_prog_clocks() const {
ccff_head_scoreboard[ccff_head_idx]++; ccff_head_scoreboard[ccff_head_idx]++;
} }
} }
if (prog_clock_ports().size() != (size_t)num_regions()) { if (prog_clock_pins().size() != (size_t)num_regions()) {
VTR_LOG_ERROR( VTR_LOG_ERROR(
"Number of programming clocks '%ld' does not match the number of " "Number of programming clocks '%ld' does not match the number of "
"configuration regions '%ld'!\n", "configuration regions '%ld'!\n",
prog_clock_ports().size(), num_regions()); prog_clock_pins().size(), num_regions());
num_err++; num_err++;
} }
for (size_t iregion = 0; iregion < ccff_head_scoreboard.size(); iregion++) { for (size_t iregion = 0; iregion < ccff_head_scoreboard.size(); iregion++) {

4
libs/libarchopenfpga/src/config_protocol.h
View File

@ -31,6 +31,8 @@ class ConfigProtocol {
CircuitModelId memory_model() const; CircuitModelId memory_model() const;
int num_regions() const; int num_regions() const;
/* Find the number of programming clocks, only valid for configuration chain type! */
size_t num_prog_clocks() const;
/* Get information of the programming clock port: name and width */ /* Get information of the programming clock port: name and width */
openfpga::BasicPort prog_clock_port_info() const; openfpga::BasicPort prog_clock_port_info() const;
/* Get a list of programming clock pins, flatten from the programming clock port */ /* Get a list of programming clock pins, flatten from the programming clock port */
@ -103,7 +105,7 @@ class ConfigProtocol {
/* Programming clock managment: This is only applicable to configuration chain /* Programming clock managment: This is only applicable to configuration chain
* protocols */ * protocols */
BasicPort prog_clk_port_; openfpga::BasicPort prog_clk_port_;
std::vector<std::vector<size_t>> prog_clk_ccff_head_indices_; std::vector<std::vector<size_t>> prog_clk_ccff_head_indices_;
char INDICE_STRING_DELIM_; char INDICE_STRING_DELIM_;

3
libs/libarchopenfpga/src/read_xml_config_protocol.cpp
View File

@ -67,7 +67,7 @@ static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk,
openfpga::BasicPort port = openfpga::PortParser(port_attr).port(); openfpga::BasicPort port = openfpga::PortParser(port_attr).port();
config_protocol.set_prog_clock_port_ccff_head_indices_pair(port, config_protocol.set_prog_clock_pin_ccff_head_indices_pair(port,
indices_attr); indices_attr);
} }
@ -207,6 +207,7 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
} }
} }
} }
config_protocol.set_prog_clock_port(prog_clk_port);
/* Second pass: fill the clock detailed connections */ /* Second pass: fill the clock detailed connections */
for (pugi::xml_node xml_progclk : xml_config_orgz.children()) { for (pugi::xml_node xml_progclk : xml_config_orgz.children()) {

4
libs/libarchopenfpga/src/write_xml_config_protocol.cpp
View File

@ -39,14 +39,14 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname,
/* CCFF protocol details */ /* CCFF protocol details */
if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) { if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
for (openfpga::BasicPort port : config_protocol.prog_clock_ports()) { for (openfpga::BasicPort port : config_protocol.prog_clock_pins()) {
fp << "\t\t\t" fp << "\t\t\t"
<< "<" << XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME; << "<" << XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME;
write_xml_attribute(fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR, write_xml_attribute(fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
port.to_verilog_string().c_str()); port.to_verilog_string().c_str());
write_xml_attribute( write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR,
config_protocol.prog_clock_port_ccff_head_indices_str(port).c_str()); config_protocol.prog_clock_pin_ccff_head_indices_str(port).c_str());
fp << "/>" fp << "/>"
<< "\n"; << "\n";
} }

2
openfpga/src/fabric/build_top_module.cpp
View File

@ -602,7 +602,7 @@ int build_top_module(
global_port_blacklist.push_back(prog_clk_port.get_name()); global_port_blacklist.push_back(prog_clk_port.get_name());
/* Add port */ /* Add port */
ModulePortId port_id = module_manager.add_port( ModulePortId port_id = module_manager.add_port(
module_id, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT); top_module, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT);
/* Add nets by following configurable children under different regions */ /* Add nets by following configurable children under different regions */
add_top_module_nets_prog_clock(module_manager, top_module, port_id, config_protocol); add_top_module_nets_prog_clock(module_manager, top_module, port_id, config_protocol);
} }

8
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -1281,13 +1281,13 @@ void add_top_module_nets_prog_clock(ModuleManager& module_manager,
const ModulePortId& src_port, const ModulePortId& src_port,
const ConfigProtocol& config_protocol) { const ConfigProtocol& config_protocol) {
BasicPort src_port_info = module_manager.module_port(top_module, src_port); BasicPort src_port_info = module_manager.module_port(top_module, src_port);
for (size_t pin : src_port_info.pins()) { for (size_t net_src_pin_id : src_port_info.pins()) {
/* Create the net */ /* Create the net */
ModuleNetId net = create_module_source_pin_net( ModuleNetId net = create_module_source_pin_net(
module_manager, top_module, top_module, 0, module_manager, top_module, top_module, 0,
src_port, src_port_info.pins()[pin_id]); src_port, src_port_info.pins()[net_src_pin_id]);
/* Find all the sink nodes and build the connection one by one */ /* Find all the sink nodes and build the connection one by one */
for (size_t iregion : config_protocol.prog_clock_port_ccff_head_indices(BasicPort(src_port_info.get_name(), pin, pin))) { for (size_t iregion : config_protocol.prog_clock_pin_ccff_head_indices(BasicPort(src_port_info.get_name(), net_src_pin_id, net_src_pin_id))) {
ConfigRegionId config_region = ConfigRegionId(iregion); ConfigRegionId config_region = ConfigRegionId(iregion);
for (size_t mem_index = 0; mem_index < module_manager for (size_t mem_index = 0; mem_index < module_manager
.region_configurable_children( .region_configurable_children(
@ -1308,7 +1308,7 @@ void add_top_module_nets_prog_clock(ModuleManager& module_manager,
/* Add net sink */ /* Add net sink */
module_manager.add_module_net_sink(top_module, net, net_sink_module_id, module_manager.add_module_net_sink(top_module, net, net_sink_module_id,
net_sink_instance_id, net_sink_port_id, net_sink_instance_id, net_sink_port_id,
net_sink_port.pins()[net_sink_pin_id]) net_sink_port.pins()[net_sink_pin_id]);
} }
} }
} }

6
openfpga/src/fabric/build_top_module_connection.h
View File

@ -6,6 +6,7 @@
*******************************************************************/ *******************************************************************/
#include <vector> #include <vector>
#include "config_protocol.h"
#include "clock_network.h" #include "clock_network.h"
#include "device_grid.h" #include "device_grid.h"
#include "device_rr_gsb.h" #include "device_rr_gsb.h"
@ -41,7 +42,10 @@ int add_top_module_global_ports_from_grid_modules(
const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk, const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup); const RRClockSpatialLookup& rr_clock_lookup);
void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, const ModulePortId& src_port, const ConfigProtocol& config_protocol); void add_top_module_nets_prog_clock(ModuleManager& module_manager,
const ModuleId& top_module,
const ModulePortId& src_port,
const ConfigProtocol& config_protocol);
} /* end namespace openfpga */ } /* end namespace openfpga */

2
openfpga/src/utils/check_config_protocol.cpp
View File

@ -34,7 +34,7 @@ static int check_config_protocol_programming_clock(
num_err++; num_err++;
} }
/* Try to match the programming clock port name with the CCFF port name */ /* Try to match the programming clock port name with the CCFF port name */
for (BasicPort prog_clk_port : config_protocol.prog_clock_ports()) { for (BasicPort prog_clk_port : config_protocol.prog_clock_pins()) {
bool port_match = false; bool port_match = false;
for (CircuitModelId ccff_model : ccff_models) { for (CircuitModelId ccff_model : ccff_models) {
CircuitPortId circuit_port = CircuitPortId circuit_port =