From bd511ba51521bc3b7a1f18cc843f7194a2928b18 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 23 Apr 2023 14:26:08 +0800 Subject: [PATCH] [core] fixed syntax errors --- libs/libarchopenfpga/src/config_protocol.cpp | 35 ++++++++++++------- libs/libarchopenfpga/src/config_protocol.h | 4 ++- .../src/read_xml_config_protocol.cpp | 3 +- .../src/write_xml_config_protocol.cpp | 4 +-- openfpga/src/fabric/build_top_module.cpp | 2 +- .../fabric/build_top_module_connection.cpp | 8 ++--- .../src/fabric/build_top_module_connection.h | 6 +++- openfpga/src/utils/check_config_protocol.cpp | 2 +- 8 files changed, 40 insertions(+), 24 deletions(-) diff --git a/libs/libarchopenfpga/src/config_protocol.cpp b/libs/libarchopenfpga/src/config_protocol.cpp index cc6031b0f..3a399d021 100644 --- a/libs/libarchopenfpga/src/config_protocol.cpp +++ b/libs/libarchopenfpga/src/config_protocol.cpp @@ -26,11 +26,18 @@ CircuitModelId ConfigProtocol::memory_model() const { return memory_model_; } int ConfigProtocol::num_regions() const { return num_regions_; } -std::vector ConfigProtocol::prog_clock_port_info() const { +size_t ConfigProtocol::num_prog_clocks() const { + VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN); + return prog_clk_port_.get_width(); +} + +openfpga::BasicPort ConfigProtocol::prog_clock_port_info() const { + VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN); return prog_clk_port_; } std::vector ConfigProtocol::prog_clock_pins() const { + VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN); std::vector keys; for (auto pin : prog_clk_port_.pins()) { keys.push_back(openfpga::BasicPort(prog_clk_port_.get_name(), pin, pin)); @@ -38,10 +45,11 @@ std::vector ConfigProtocol::prog_clock_pins() const { return keys; } -std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str( +std::string ConfigProtocol::prog_clock_pin_ccff_head_indices_str( const openfpga::BasicPort& port) const { + VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN); std::string ret(""); - std::vector raw = prog_clock_port_ccff_head_indices(port); + std::vector raw = prog_clock_pin_ccff_head_indices(port); if (!raw.empty()) { for (size_t idx : raw) { /* TODO: We need a join function */ @@ -53,13 +61,14 @@ std::string ConfigProtocol::prog_clock_port_ccff_head_indices_str( return ret; } -std::vector ConfigProtocol::prog_clock_port_ccff_head_indices( +std::vector ConfigProtocol::prog_clock_pin_ccff_head_indices( const openfpga::BasicPort& port) const { + VTR_ASSERT(type_ == CONFIG_MEM_SCAN_CHAIN); std::vector ret; if (port.get_width() != 1) { VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width()); } - VTR_ASSERT(port.get_width == 1); + VTR_ASSERT(port.get_width() == 1); if (!prog_clk_port_.contained(port)) { VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb()); } @@ -115,12 +124,12 @@ void ConfigProtocol::set_num_regions(const int& num_regions) { num_regions_ = num_regions; } -void ConfigProtocol::set_prog_clock(const openfpga::BasicPort& port) { +void ConfigProtocol::set_prog_clock_port(const openfpga::BasicPort& port) { prog_clk_port_ = port; prog_clk_ccff_head_indices_.resize(prog_clk_port_.get_width()); } -void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair( +void ConfigProtocol::set_prog_clock_pin_ccff_head_indices_pair( const openfpga::BasicPort& port, const std::string& indices_str) { openfpga::StringToken tokenizer(indices_str); std::vector token_int; @@ -131,7 +140,7 @@ void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair( if (port.get_width() != 1) { VTR_LOG_ERROR("The programming clock pin must have a width of 1 while the width specified is %ld!\n", port.get_width()); } - VTR_ASSERT(port.get_width == 1); + VTR_ASSERT(port.get_width() == 1); if (!prog_clk_port_.contained(port)) { VTR_LOG_ERROR("The programming clock pin '%s[%ld]' is not out of the range [%ld, %ld]!\n", port.get_name().c_str(), port.get_lsb(), prog_clk_port_.get_lsb(), prog_clk_port_.get_msb()); } @@ -141,7 +150,7 @@ void ConfigProtocol::set_prog_clock_port_ccff_head_indices_pair( "Overwrite the pair between programming clock port '%s[%d:%d]' and ccff " "head indices (previous: '%s', current: '%s')!\n", port.get_name().c_str(), port.get_lsb(), port.get_msb(), - prog_clock_port_ccff_head_indices_str(port).c_str(), indices_str.c_str()); + prog_clock_pin_ccff_head_indices_str(port).c_str(), indices_str.c_str()); } prog_clk_ccff_head_indices_[port.get_lsb()] = token_int; } @@ -235,7 +244,7 @@ int ConfigProtocol::validate_ccff_prog_clocks() const { int num_err = 0; /* Initialize scoreboard */ std::vector ccff_head_scoreboard(num_regions(), 0); - for (openfpga::BasicPort port : prog_clock_ports()) { + for (openfpga::BasicPort port : prog_clock_pins()) { /* Must be valid first */ if (port.is_valid()) { VTR_LOG_ERROR("Programming clock '%s[%d:%d]' is not a valid port!\n", @@ -251,7 +260,7 @@ int ConfigProtocol::validate_ccff_prog_clocks() const { num_err++; } /* Fill scoreboard */ - for (size_t ccff_head_idx : prog_clock_port_ccff_head_indices(port)) { + for (size_t ccff_head_idx : prog_clock_pin_ccff_head_indices(port)) { if (ccff_head_idx >= ccff_head_scoreboard.size()) { VTR_LOG_ERROR( "Programming clock '%s[%d:%d]' controlls an invalid ccff head '%ld' " @@ -263,11 +272,11 @@ int ConfigProtocol::validate_ccff_prog_clocks() const { ccff_head_scoreboard[ccff_head_idx]++; } } - if (prog_clock_ports().size() != (size_t)num_regions()) { + if (prog_clock_pins().size() != (size_t)num_regions()) { VTR_LOG_ERROR( "Number of programming clocks '%ld' does not match the number of " "configuration regions '%ld'!\n", - prog_clock_ports().size(), num_regions()); + prog_clock_pins().size(), num_regions()); num_err++; } for (size_t iregion = 0; iregion < ccff_head_scoreboard.size(); iregion++) { diff --git a/libs/libarchopenfpga/src/config_protocol.h b/libs/libarchopenfpga/src/config_protocol.h index 4e345bb1f..d80135eb3 100644 --- a/libs/libarchopenfpga/src/config_protocol.h +++ b/libs/libarchopenfpga/src/config_protocol.h @@ -31,6 +31,8 @@ class ConfigProtocol { CircuitModelId memory_model() const; int num_regions() const; + /* Find the number of programming clocks, only valid for configuration chain type! */ + size_t num_prog_clocks() const; /* Get information of the programming clock port: name and width */ openfpga::BasicPort prog_clock_port_info() const; /* Get a list of programming clock pins, flatten from the programming clock port */ @@ -103,7 +105,7 @@ class ConfigProtocol { /* Programming clock managment: This is only applicable to configuration chain * protocols */ - BasicPort prog_clk_port_; + openfpga::BasicPort prog_clk_port_; std::vector> prog_clk_ccff_head_indices_; char INDICE_STRING_DELIM_; diff --git a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp index 3ac930bad..b1d9acd76 100644 --- a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -67,7 +67,7 @@ static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk, openfpga::BasicPort port = openfpga::PortParser(port_attr).port(); - config_protocol.set_prog_clock_port_ccff_head_indices_pair(port, + config_protocol.set_prog_clock_pin_ccff_head_indices_pair(port, indices_attr); } @@ -207,6 +207,7 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz, } } } + config_protocol.set_prog_clock_port(prog_clk_port); /* Second pass: fill the clock detailed connections */ for (pugi::xml_node xml_progclk : xml_config_orgz.children()) { diff --git a/libs/libarchopenfpga/src/write_xml_config_protocol.cpp b/libs/libarchopenfpga/src/write_xml_config_protocol.cpp index 9690c629f..f721e6885 100644 --- a/libs/libarchopenfpga/src/write_xml_config_protocol.cpp +++ b/libs/libarchopenfpga/src/write_xml_config_protocol.cpp @@ -39,14 +39,14 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname, /* CCFF protocol details */ if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) { - for (openfpga::BasicPort port : config_protocol.prog_clock_ports()) { + for (openfpga::BasicPort port : config_protocol.prog_clock_pins()) { fp << "\t\t\t" << "<" << XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME; write_xml_attribute(fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR, port.to_verilog_string().c_str()); write_xml_attribute( fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, - config_protocol.prog_clock_port_ccff_head_indices_str(port).c_str()); + config_protocol.prog_clock_pin_ccff_head_indices_str(port).c_str()); fp << "/>" << "\n"; } diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 11187c068..b333a8010 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -602,7 +602,7 @@ int build_top_module( global_port_blacklist.push_back(prog_clk_port.get_name()); /* Add port */ ModulePortId port_id = module_manager.add_port( - module_id, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT); + top_module, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT); /* Add nets by following configurable children under different regions */ add_top_module_nets_prog_clock(module_manager, top_module, port_id, config_protocol); } diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 0b51e7f06..f25db810d 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1281,13 +1281,13 @@ void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModulePortId& src_port, const ConfigProtocol& config_protocol) { BasicPort src_port_info = module_manager.module_port(top_module, src_port); - for (size_t pin : src_port_info.pins()) { + for (size_t net_src_pin_id : src_port_info.pins()) { /* Create the net */ ModuleNetId net = create_module_source_pin_net( module_manager, top_module, top_module, 0, - src_port, src_port_info.pins()[pin_id]); + src_port, src_port_info.pins()[net_src_pin_id]); /* Find all the sink nodes and build the connection one by one */ - for (size_t iregion : config_protocol.prog_clock_port_ccff_head_indices(BasicPort(src_port_info.get_name(), pin, pin))) { + for (size_t iregion : config_protocol.prog_clock_pin_ccff_head_indices(BasicPort(src_port_info.get_name(), net_src_pin_id, net_src_pin_id))) { ConfigRegionId config_region = ConfigRegionId(iregion); for (size_t mem_index = 0; mem_index < module_manager .region_configurable_children( @@ -1308,7 +1308,7 @@ void add_top_module_nets_prog_clock(ModuleManager& module_manager, /* Add net sink */ module_manager.add_module_net_sink(top_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, - net_sink_port.pins()[net_sink_pin_id]) + net_sink_port.pins()[net_sink_pin_id]); } } } diff --git a/openfpga/src/fabric/build_top_module_connection.h b/openfpga/src/fabric/build_top_module_connection.h index 66b96abab..0fcb99668 100644 --- a/openfpga/src/fabric/build_top_module_connection.h +++ b/openfpga/src/fabric/build_top_module_connection.h @@ -6,6 +6,7 @@ *******************************************************************/ #include +#include "config_protocol.h" #include "clock_network.h" #include "device_grid.h" #include "device_rr_gsb.h" @@ -41,7 +42,10 @@ int add_top_module_global_ports_from_grid_modules( const vtr::Matrix& grid_instance_ids, const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup); -void add_top_module_nets_prog_clock(ModuleManager& module_manager, const ModuleId& top_module, const ModulePortId& src_port, const ConfigProtocol& config_protocol); +void add_top_module_nets_prog_clock(ModuleManager& module_manager, + const ModuleId& top_module, + const ModulePortId& src_port, + const ConfigProtocol& config_protocol); } /* end namespace openfpga */ diff --git a/openfpga/src/utils/check_config_protocol.cpp b/openfpga/src/utils/check_config_protocol.cpp index 247bb5a48..42dc99c51 100644 --- a/openfpga/src/utils/check_config_protocol.cpp +++ b/openfpga/src/utils/check_config_protocol.cpp @@ -34,7 +34,7 @@ static int check_config_protocol_programming_clock( num_err++; } /* Try to match the programming clock port name with the CCFF port name */ - for (BasicPort prog_clk_port : config_protocol.prog_clock_ports()) { + for (BasicPort prog_clk_port : config_protocol.prog_clock_pins()) { bool port_match = false; for (CircuitModelId ccff_model : ccff_models) { CircuitPortId circuit_port =