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[Architecture] Rename AIB architecture for the new cell naming

This commit is contained in:
tangxifan 2020-09-24 20:14:16 -06:00
parent 8edfc79f53
commit bd0f0144a0
2 changed files with 10 additions and 10 deletions
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8
openfpga_flow/VerilogNetlists/aib.v
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@ -6,11 +6,11 @@
//----------------------------------------------------- //-----------------------------------------------------
module AIB ( module AIB (
input TXCLK, input TX_CLK,
input RXCLK, input RX_CLK,
inout[0:79] PAD, inout[0:79] PAD,
input[0:79] TXDATA, input[0:79] TX_DATA,
output[0:79] RXDATA); output[0:79] RX_DATA);
// May add the logic function of a real AIB // May add the logic function of a real AIB
// Refer to the offical AIB github // Refer to the offical AIB github

12
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -206,14 +206,14 @@
<port type="output" prefix="d_out" size="32"/> <port type="output" prefix="d_out" size="32"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/> <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v"> <circuit_model type="iopad" name="AIB" prefix="AIB" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="tx_data" size="80"/> <port type="input" prefix="tx_data" lib_name="TX_DATA" size="80"/>
<port type="output" prefix="rx_data" size="80"/> <port type="output" prefix="rx_data" lib_name="RX_DATA" size="80"/>
<port type="clock" prefix="tx_clk" size="1" default_val="0"/> <port type="clock" prefix="tx_clk" lib_name="TX_CLK" size="1" default_val="0"/>
<port type="clock" prefix="rx_clk" size="1" default_val="0"/> <port type="clock" prefix="rx_clk" lib_name="RX_CLK" size="1" default_val="0"/>
<port type="inout" prefix="PAD" size="80" is_global="true" is_io="true"/> <port type="inout" prefix="PAD" size="80" is_global="true" is_io="true"/>
</circuit_model> </circuit_model>
</circuit_library> </circuit_library>
@ -234,7 +234,7 @@
</direct_connection> </direct_connection>
<pb_type_annotations> <pb_type_annotations>
<!-- physical pb_type binding in complex block AIB--> <!-- physical pb_type binding in complex block AIB-->
<pb_type name="aib[physical].aib_core" circuit_model_name="aib"/> <pb_type name="aib[physical].aib_core" circuit_model_name="AIB"/>
<!-- physical pb_type binding in complex block IO --> <!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>