From bd0f0144a0724ffcfe4dd0fd514f00c077cb2750 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 24 Sep 2020 20:14:16 -0600
Subject: [PATCH] [Architecture] Rename AIB architecture for the new cell
 naming

---
 openfpga_flow/VerilogNetlists/aib.v                  |  8 ++++----
 ...frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml | 12 ++++++------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v
index 86ea4f671..8d1b9e6da 100644
--- a/openfpga_flow/VerilogNetlists/aib.v
+++ b/openfpga_flow/VerilogNetlists/aib.v
@@ -6,11 +6,11 @@
 //-----------------------------------------------------
 
 module AIB (
-	input TXCLK,
-	input RXCLK,
+	input TX_CLK,
+	input RX_CLK,
 	inout[0:79] PAD,
-	input[0:79] TXDATA,
-	output[0:79] RXDATA);
+	input[0:79] TX_DATA,
+	output[0:79] RX_DATA);
 
 // May add the logic function of a real AIB
 // Refer to the offical AIB github
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index 34474e19e..c1a7d8d3d 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -206,14 +206,14 @@
       <port type="output" prefix="d_out" size="32"/>
       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
     </circuit_model>
-    <circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
+    <circuit_model type="iopad" name="AIB" prefix="AIB" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="tx_data" size="80"/>
-      <port type="output" prefix="rx_data" size="80"/>
-      <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
-      <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
+      <port type="input" prefix="tx_data" lib_name="TX_DATA" size="80"/>
+      <port type="output" prefix="rx_data" lib_name="RX_DATA" size="80"/>
+      <port type="clock" prefix="tx_clk" lib_name="TX_CLK" size="1" default_val="0"/>
+      <port type="clock" prefix="rx_clk" lib_name="RX_CLK" size="1" default_val="0"/>
       <port type="inout" prefix="PAD" size="80" is_global="true" is_io="true"/>
     </circuit_model>
   </circuit_library>
@@ -234,7 +234,7 @@
   </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block AIB-->
-    <pb_type name="aib[physical].aib_core" circuit_model_name="aib"/>
+    <pb_type name="aib[physical].aib_core" circuit_model_name="AIB"/>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
     <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>