riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled

This commit is contained in:
tangxifan 2024-07-03 22:28:22 -07:00
parent 3d19e10611
commit bc94e08c77
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -420,6 +420,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
*/ */
vtr::Point<size_t> gsb_range(vpr_device_ctx.grid.width() - 1, vtr::Point<size_t> gsb_range(vpr_device_ctx.grid.width() - 1,
vpr_device_ctx.grid.height() - 1); vpr_device_ctx.grid.height() - 1);
if (vpr_device_ctx.arch->perimeter_cb) {
gsb_range.set(vpr_device_ctx.grid.width(), vpr_device_ctx.grid.height());
}
device_rr_gsb.reserve(gsb_range); device_rr_gsb.reserve(gsb_range);
VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n", VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n",
@ -434,10 +437,14 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
* the GSBs at the borderside correctly sort drive_rr_nodes should be * the GSBs at the borderside correctly sort drive_rr_nodes should be
* called if required by users * called if required by users
*/ */
vtr::Point<size_t> sub_gsb_range(vpr_device_ctx.grid.width() - 2,
vpr_device_ctx.grid.height() - 2);
if (vpr_device_ctx.arch->perimeter_cb) {
sub_gsb_range.set(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1);
}
const RRGSB& rr_gsb = const RRGSB& rr_gsb =
build_rr_gsb(vpr_device_ctx, build_rr_gsb(vpr_device_ctx,
vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2, sub_gsb_range,
vpr_device_ctx.grid.height() - 2),
layer, vtr::Point<size_t>(ix, iy), include_clock); layer, vtr::Point<size_t>(ix, iy), include_clock);
/* Add to device_rr_gsb */ /* Add to device_rr_gsb */
vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate(); vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate();

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 Subproject commit 7aa23041f18ce07a10b62fa7459166f613d039d2