From bc94e08c77cdef86b84149f11892e02bd00bfb53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2024 22:28:22 -0700 Subject: [PATCH] [lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled --- openfpga/src/annotation/annotate_rr_graph.cpp | 11 +++++++++-- vtr-verilog-to-routing | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 291d9cd9b..613364de2 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -420,6 +420,9 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, */ vtr::Point gsb_range(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + if (vpr_device_ctx.arch->perimeter_cb) { + gsb_range.set(vpr_device_ctx.grid.width(), vpr_device_ctx.grid.height()); + } device_rr_gsb.reserve(gsb_range); VTR_LOGV(verbose_output, "Start annotation GSB up to [%lu][%lu]\n", @@ -434,10 +437,14 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx, * the GSBs at the borderside correctly sort drive_rr_nodes should be * called if required by users */ + vtr::Point sub_gsb_range(vpr_device_ctx.grid.width() - 2, + vpr_device_ctx.grid.height() - 2); + if (vpr_device_ctx.arch->perimeter_cb) { + sub_gsb_range.set(vpr_device_ctx.grid.width() - 1, vpr_device_ctx.grid.height() - 1); + } const RRGSB& rr_gsb = build_rr_gsb(vpr_device_ctx, - vtr::Point(vpr_device_ctx.grid.width() - 2, - vpr_device_ctx.grid.height() - 2), + sub_gsb_range, layer, vtr::Point(ix, iy), include_clock); /* Add to device_rr_gsb */ vtr::Point gsb_coordinate = rr_gsb.get_sb_coordinate(); diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 64bbd2454..7aa23041f 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 64bbd2454e81ea4790b27a7846cd5e454f5bc3f9 +Subproject commit 7aa23041f18ce07a10b62fa7459166f613d039d2