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[engine] update vtr and add in_edge checks to link_arch

This commit is contained in:
tangxifan 2022-08-24 12:22:20 -07:00
parent f7311857c7
commit ba6ae05091
2 changed files with 5 additions and 1 deletions
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4
openfpga/src/base/openfpga_link_arch.cpp
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@ -129,6 +129,10 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }
/* Build incoming edges as VPR only builds fan-out edges for each node */
g_vpr_ctx.mutable_device().rr_graph_builder.build_in_edges();
VTR_LOG("Built %ld incoming edges for routing resource graph\n", g_vpr_ctx.device().rr_graph.in_edges_count());
VTR_ASSERT(g_vpr_ctx.device().rr_graph.validate_in_edges());
annotate_device_rr_gsb(g_vpr_ctx.device(), annotate_device_rr_gsb(g_vpr_ctx.device(),
openfpga_ctx.mutable_device_rr_gsb(), openfpga_ctx.mutable_device_rr_gsb(),
cmd_context.option_enable(cmd, opt_verbose)); cmd_context.option_enable(cmd, opt_verbose));

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit c16fcb8fba16b45484e5c41db506533ee706e986 Subproject commit 3ca5e2f221c78742d0893209e07c6d084c0ef730