From ba6ae05091eec5fc23695f0b27afa564d12ddb84 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 24 Aug 2022 12:22:20 -0700 Subject: [PATCH] [engine] update vtr and add in_edge checks to link_arch --- openfpga/src/base/openfpga_link_arch.cpp | 4 ++++ vtr-verilog-to-routing | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_link_arch.cpp b/openfpga/src/base/openfpga_link_arch.cpp index ef24e65bb..002c3bfc1 100644 --- a/openfpga/src/base/openfpga_link_arch.cpp +++ b/openfpga/src/base/openfpga_link_arch.cpp @@ -129,6 +129,10 @@ int link_arch(OpenfpgaContext& openfpga_ctx, return CMD_EXEC_FATAL_ERROR; } + /* Build incoming edges as VPR only builds fan-out edges for each node */ + g_vpr_ctx.mutable_device().rr_graph_builder.build_in_edges(); + VTR_LOG("Built %ld incoming edges for routing resource graph\n", g_vpr_ctx.device().rr_graph.in_edges_count()); + VTR_ASSERT(g_vpr_ctx.device().rr_graph.validate_in_edges()); annotate_device_rr_gsb(g_vpr_ctx.device(), openfpga_ctx.mutable_device_rr_gsb(), cmd_context.option_enable(cmd, opt_verbose)); diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index c16fcb8fb..3ca5e2f22 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit c16fcb8fba16b45484e5c41db506533ee706e986 +Subproject commit 3ca5e2f221c78742d0893209e07c6d084c0ef730