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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA

This commit is contained in:
Baudouin Chauviere 2018-12-10 13:48:09 -07:00
parent 1472e7aa62 55459f7906
commit ba6ace343b
6 changed files with 19 additions and 22 deletions
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3
.gitmodules vendored
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@ -1,6 +1,3 @@
[submodule "tangxifan-eda-tools"]
path = tangxifan-eda-tools
url = https://github.com/tangxifan/tangxifan-eda-tools.git
[submodule "OpenSTA"] [submodule "OpenSTA"]
path = OpenSTA path = OpenSTA
url = https://github.com/abk-openroad/OpenSTA url = https://github.com/abk-openroad/OpenSTA

15
docs/source/index.rst
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@ -6,12 +6,6 @@
Welcome to OpenFPGA's documentation! Welcome to OpenFPGA's documentation!
==================================== ====================================
For more information on the ABC see abc_doc_ // abc_github_
For more information on the VTR see vtr_doc_ // vtr_github_
For more information on the original FPGA architecture description language see xml_vtr_
.. toctree:: .. toctree::
:caption: Motivation :caption: Motivation
@ -47,7 +41,11 @@ For more information on the original FPGA architecture description language see
contact contact
reference reference
For more information on the VTR see vtr_doc_ // vtr_github_
For more information on the Yosys see yosys_doc_ // yosys_github_
For more information on the original FPGA architecture description language see xml_vtr_
@ -58,9 +56,8 @@ Indices and tables
* :ref:`modindex` * :ref:`modindex`
* :ref:`search` * :ref:`search`
.. _yosys_doc: http://www.clifford.at/yosys/
.. _abc_doc: https://people.eecs.berkeley.edu/~alanmi/abc/ .. _yosys_github: https://github.com/YosysHQ/yosys
.. _abc_github: https://github.com/berkeley-abc/abc
.. _vpr_doc: https://docs.verilogtorouting.org/en/latest/ .. _vpr_doc: https://docs.verilogtorouting.org/en/latest/
.. _vpr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing .. _vpr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/ .. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/

15
fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
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@ -174,7 +174,7 @@
</input> </input>
</stimulate> </stimulate>
</parameters> </parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/> <tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M"> <transistors pn_ratio="2" model_ref="M">
<nmos model_name="nmos" chan_length="45e-9" min_width="140e-9"/> <nmos model_name="nmos" chan_length="45e-9" min_width="140e-9"/>
<pmos model_name="pmos" chan_length="45e-9" min_width="140e-9"/> <pmos model_name="pmos" chan_length="45e-9" min_width="140e-9"/>
@ -254,7 +254,7 @@
<port type="sram" prefix="sram" size="1"/> <port type="sram" prefix="sram" size="1"/>
</circuit_model> </circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v"> <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/> <input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/> <output_buffer exist="on" circuit_model_name="INVTX1"/>
@ -275,7 +275,7 @@
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64"/> <port type="sram" prefix="sram" size="64"/>
</circuit_model> </circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v" > <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v" >
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/> <input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/> <output_buffer exist="on" circuit_model_name="INVTX1"/>
@ -283,8 +283,7 @@
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/> <port type="output" prefix="out" size="2"/>
</circuit_model> </circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v"> <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/> <input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/> <output_buffer exist="on" circuit_model_name="INVTX1"/>
@ -296,7 +295,7 @@
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/> <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
</circuit_model> </circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="sff" name="sc_ff" prefix="scff" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v"> <circuit_model type="sff" name="sc_dff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/> <input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/> <output_buffer exist="on" circuit_model_name="INVTX1"/>
@ -307,7 +306,7 @@
<port type="output" prefix="Q" size="2"/> <port type="output" prefix="Q" size="2"/>
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model> </circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/home/u6017869/Documents/newer_OpenFPGA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/io.v"> <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/> <input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/> <output_buffer exist="on" circuit_model_name="INVTX1"/>
@ -347,7 +346,7 @@
<!-- Choose only one organization, either the scan chain or the memory decoder --> <!-- Choose only one organization, either the scan chain or the memory decoder -->
<sram area="6"> <sram area="6">
<verilog organization="scan-chain" circuit_model_name="sc_ff" /> <verilog organization="scan-chain" circuit_model_name="sc_dff" />
<spice organization="standalone" circuit_model_name="sram6T" /> <spice organization="standalone" circuit_model_name="sram6T" />
</sram> </sram>
<!-- Uncomment to get the memory bank // Comment the scan-chain--> <!-- Uncomment to get the memory bank // Comment the scan-chain-->

2
vpr7_x2p/vpr/SRC/base/read_blif.c
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@ -523,6 +523,8 @@ static void add_latch(int doall, INP t_model *latch_model) {
logical_block[num_logical_blocks - 1].trigger_type = my_strdup(saved_names[2]); logical_block[num_logical_blocks - 1].trigger_type = my_strdup(saved_names[2]);
/* Store the initial value */ /* Store the initial value */
logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]); logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]);
/* Identify clocks */
logical_block[logical_block[num_logical_blocks - 1].clock_net].is_clock = TRUE;
/*END*/ /*END*/
num_latches++; num_latches++;

2
vpr7_x2p/vpr/SRC/base/vpr_types.h
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@ -248,6 +248,8 @@ typedef struct s_logical_block {
/* for Register/flip-flop */ /* for Register/flip-flop */
char* trigger_type; char* trigger_type;
int init_val; int init_val;
/* To identify if this is a clock */
int is_clock;
} t_logical_block; } t_logical_block;

4
vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c
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@ -6915,7 +6915,7 @@ void stats_spice_muxes_routing_arch(t_llist** muxes_head,
case IPIN: case IPIN:
/* Have to consider the fan_in only, it is a connection box(multiplexer)*/ /* Have to consider the fan_in only, it is a connection box(multiplexer)*/
assert((node->fan_in > 0)||(0 == node->fan_in)); assert((node->fan_in > 0)||(0 == node->fan_in));
if (0 == node->fan_in) { if ((0 == node->fan_in)||(1 == node->fan_in)) {
break; break;
} }
/* Find the spice_model for multiplexers in connection blocks */ /* Find the spice_model for multiplexers in connection blocks */
@ -6931,7 +6931,7 @@ void stats_spice_muxes_routing_arch(t_llist** muxes_head,
* or it could be a connection box if previous rr_node is a IPIN or OPIN * or it could be a connection box if previous rr_node is a IPIN or OPIN
*/ */
assert((node->fan_in > 0)||(0 == node->fan_in)); assert((node->fan_in > 0)||(0 == node->fan_in));
if (0 == node->fan_in) { if ((0 == node->fan_in)||(1 == node->fan_in)) {
break; break;
} }
/* Find the spice_model for multiplexers in switch blocks*/ /* Find the spice_model for multiplexers in switch blocks*/