From 7bcc61b0f273102f9889dbef54d6e13c6670e4c4 Mon Sep 17 00:00:00 2001 From: LNIS-Projects <40280375+LNIS-Projects@users.noreply.github.com> Date: Mon, 10 Dec 2018 12:07:05 -0700 Subject: [PATCH 1/4] Update .gitmodules Unused submodule blocking the compilation of the documentation --- .gitmodules | 3 --- 1 file changed, 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index e97e70723..bb17c5f21 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,3 @@ -[submodule "tangxifan-eda-tools"] - path = tangxifan-eda-tools - url = https://github.com/tangxifan/tangxifan-eda-tools.git [submodule "OpenSTA"] path = OpenSTA url = https://github.com/abk-openroad/OpenSTA From 72fbd8d6a8471b6e755e1ccfea950d25db5debf8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 10 Dec 2018 13:28:44 -0700 Subject: [PATCH 2/4] update blif reader to identify clock signals --- .../arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml | 15 +++++++-------- vpr7_x2p/vpr/SRC/base/read_blif.c | 2 ++ vpr7_x2p/vpr/SRC/base/vpr_types.h | 2 ++ .../vpr/SRC/fpga_spice/base/fpga_spice_utils.c | 4 ++-- 4 files changed, 13 insertions(+), 10 deletions(-) diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml index eee87e4e5..5b409067d 100755 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml @@ -174,7 +174,7 @@ - + @@ -254,7 +254,7 @@ - + @@ -275,7 +275,7 @@ - + @@ -283,8 +283,7 @@ - - + @@ -296,7 +295,7 @@ - + @@ -307,7 +306,7 @@ - + @@ -347,7 +346,7 @@ - + diff --git a/vpr7_x2p/vpr/SRC/base/read_blif.c b/vpr7_x2p/vpr/SRC/base/read_blif.c index c369a5a93..cabea82e9 100644 --- a/vpr7_x2p/vpr/SRC/base/read_blif.c +++ b/vpr7_x2p/vpr/SRC/base/read_blif.c @@ -523,6 +523,8 @@ static void add_latch(int doall, INP t_model *latch_model) { logical_block[num_logical_blocks - 1].trigger_type = my_strdup(saved_names[2]); /* Store the initial value */ logical_block[num_logical_blocks - 1].init_val = my_atoi(saved_names[4]); + /* Identify clocks */ + logical_block[logical_block[num_logical_blocks - 1].clock_net].is_clock = TRUE; /*END*/ num_latches++; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index cfa790ec2..f1f21dece 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -248,6 +248,8 @@ typedef struct s_logical_block { /* for Register/flip-flop */ char* trigger_type; int init_val; + /* To identify if this is a clock */ + int is_clock; } t_logical_block; diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c b/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c index 374d86f5d..eb13ff2cb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_spice/base/fpga_spice_utils.c @@ -6915,7 +6915,7 @@ void stats_spice_muxes_routing_arch(t_llist** muxes_head, case IPIN: /* Have to consider the fan_in only, it is a connection box(multiplexer)*/ assert((node->fan_in > 0)||(0 == node->fan_in)); - if (0 == node->fan_in) { + if ((0 == node->fan_in)||(1 == node->fan_in)) { break; } /* Find the spice_model for multiplexers in connection blocks */ @@ -6931,7 +6931,7 @@ void stats_spice_muxes_routing_arch(t_llist** muxes_head, * or it could be a connection box if previous rr_node is a IPIN or OPIN */ assert((node->fan_in > 0)||(0 == node->fan_in)); - if (0 == node->fan_in) { + if ((0 == node->fan_in)||(1 == node->fan_in)) { break; } /* Find the spice_model for multiplexers in switch blocks*/ From 56555fc8a0a8e703ca7f2f8b7034f3bdc8939275 Mon Sep 17 00:00:00 2001 From: LNIS-Projects <40280375+LNIS-Projects@users.noreply.github.com> Date: Mon, 10 Dec 2018 13:46:02 -0700 Subject: [PATCH 3/4] Update index.rst Removed abc from the project because included in Yosys --- docs/source/index.rst | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/docs/source/index.rst b/docs/source/index.rst index ee38f2bbe..ce536a926 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -6,10 +6,8 @@ Welcome to OpenFPGA's documentation! ==================================== -For more information on the ABC see abc_doc_ // abc_github_ - For more information on the VTR see vtr_doc_ // vtr_github_ - +For more information on the Yosys see yosys_doc_ // yosys_github_ For more information on the original FPGA architecture description language see xml_vtr_ .. toctree:: @@ -58,9 +56,8 @@ Indices and tables * :ref:`modindex` * :ref:`search` - -.. _abc_doc: https://people.eecs.berkeley.edu/~alanmi/abc/ -.. _abc_github: https://github.com/berkeley-abc/abc +.. _yosys_doc: http://www.clifford.at/yosys/ +.. _yosys_github: https://github.com/YosysHQ/yosys .. _vpr_doc: https://docs.verilogtorouting.org/en/latest/ .. _vpr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing .. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/ From 55459f790611bb186007806f30e1db11f6f67279 Mon Sep 17 00:00:00 2001 From: LNIS-Projects <40280375+LNIS-Projects@users.noreply.github.com> Date: Mon, 10 Dec 2018 13:46:38 -0700 Subject: [PATCH 4/4] Update index.rst Reorganization --- docs/source/index.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/source/index.rst b/docs/source/index.rst index ce536a926..527533a77 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -6,10 +6,6 @@ Welcome to OpenFPGA's documentation! ==================================== -For more information on the VTR see vtr_doc_ // vtr_github_ -For more information on the Yosys see yosys_doc_ // yosys_github_ -For more information on the original FPGA architecture description language see xml_vtr_ - .. toctree:: :caption: Motivation @@ -45,7 +41,11 @@ For more information on the original FPGA architecture description language see contact reference +For more information on the VTR see vtr_doc_ // vtr_github_ +For more information on the Yosys see yosys_doc_ // yosys_github_ + +For more information on the original FPGA architecture description language see xml_vtr_